Kiran Ramineni

Automatic generation of functional coverage models from CTL

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Evaluation of an efficient control-oriented coverage metric

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Improving feasible interactions among multiple processes

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

An efficient control-oriented coverage metric

I.G. Harris, S. Verma, K. Ramineni, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

An efficient control-oriented coverage metric

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A Control-Oriented Coverage Metric and its Evaluation for Hardware Designs

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2009 .

Verifying Complex Interaction between Hardware Processes

Ian G. Harris, Shireesh Verma, Kiran Ramineni, 2009 .

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

I. Harris, Shireesh Verma, Kiran Ramineni, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.