S. Odanaka

发表

A New Half-Micron P-Channel MOS FET with Efficient Punchthrough Stops

M. Sasago, T. Ohzone, S. Odanaka, 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

HiSIM: a drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction

S. Kumashiro, H.J. Mattausch, M. Miura-Mattausch, 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

Low voltage, low current, high speed program step split gate cell with ballistic direct injection for EEPROM/flash

T. Ogura, K. Akamatsu, S. Odanaka, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

A. Amerasekera, H. Masuda, S.-W. Lee, 2007, 2007 IEEE Symposium on VLSI Technology.

A Three-Dimensional Process Simulation using Advanced SMART-P program

S. Odanaka, H. Umimoto, A. Gohda, 1995 .

Three-Dimensional Numerical Modeling of the Indirect Band-to-Band Tunneling in MOSFET's

S. Odanaka, Y. Odake, K. Kurimoto, 1990 .

The inverse-narrow-width effect of LOCOS isolated n-MOSFET in a high-concentration p-well

T. Yabu, S. Odanaka, H. Umimoto, 1992, IEEE Electron Device Letters.

Potential design and transport property of 0.1-/spl mu/m MOSFET with asymmetric channel profile

S. Odanaka, S. Odanaka, A. Hiroki, 1997 .

Gate-oxide thickness dependence of hot-carrier-induced degradation in buried p-MOSFETs

S. Odanaka, A. Hiroki, 1990, International Technical Digest on Electron Devices.

A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

M. Sasago, T. Ohzone, S. Odanaka, 1987, IEEE Transactions on Electron Devices.

Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal–oxide–semiconductor field-effect transistors

Hans Jurgen Mattausch, Mitiko Miura-Mattausch, S. Kumashiro, 2002 .

Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages

M. Sasago, T. Ohzone, T. Yabu, 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

A practical trench isolation technology with a novel planarization process

T. Ohzone, S. Odanaka, K. Tateiwa, 1987, 1987 International Electron Devices Meeting.

A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation

S. Odanaka, K. Ohe, A. Hiroki, 1988 .

Numerical simulation of stress-dependent oxide growth at convex and concave corners of trench structures

S. Odanaka, H. Umimoto, I. Nakao, 1989, IEEE Electron Device Letters.

Validity of mobility universality for scaled metal–oxide–semiconductor field-effect transistors down to 100 nm gate length

Hans Jurgen Mattausch, S. Kumashiro, M. Miura-Mattausch, 2002 .

Physical modeling of the reverse-short-channel effect for circuit simulation

Hans Jurgen Mattausch, Mitiko Miura-Mattausch, S. Kumashiro, 2001 .

Impact of crosstalk on delay time and a hierarchy of interconnects

K. Yamashita, S. Odanaka, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A self-aligned retrograde twin-well structure with buried p/sup +/-layer

T. Ohzone, T. Yabu, S. Odanaka, 1989, IEEE Electron Device Letters.

Three-dimensional numerical simulation of local oxidation of silicon

S. Odanaka, H. Umimoto, H. Umimoto, 1991 .

Drain leakage current characteristics due to the band-to-band tunneling in LDD MOS devices

S. Odanaka, Y. Odake, K. Kurimoto, 1989, International Technical Digest on Electron Devices Meeting.

Gate-oxide thickness dependence of hot-carrier-induced degradation in buried p-MOSFET's

S. Odanaka, A. Hiroki, 1992 .

Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applications

M. Sasago, T. Ohzone, S. Odanaka, 1985, IEEE Transactions on Electron Devices.

A T-gate overlapped LDD device with high circuit performance and high reliability

S. Odanaka, S. Odanaka, K. Kurimoto, 1991, International Electron Devices Meeting 1991 [Technical Digest].

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

M. Sasago, T. Ohzone, T. Yabu, 1986, IEEE Transactions on Electron Devices.

Narrow-width effects of shallow trench-isolated CMOS with n/sup +/-polysilicon gate

S. Odanaka, K. Moriyama, Genshu Fuse, 1989 .

Precise physical modeling of the reverse-short-channel effect for circuit simulation

S. Kumashiro, M. Miura-Mattausch, N. Shigyo, 1999, 1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387).

The dynamics of latchup turn-on behavior in scaled CMOS

T. Ohzone, S. Odanaka, S. Odanaka, 1985, IEEE Transactions on Electron Devices.