H. Yamauchi

A 16mb Dram with an Open Bit-Line Architecture

T. Yamada, H. Akamatsu, M. Inoue, 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

3D vision system for spherical objects using highlight patterns

H. Yamauchi, N. Aoki, T. Inari, 2003, SICE 2003 Annual Conference (IEEE Cat. No.03TH8734).

A SINGLE CHIP MPEGI DECODER

Shigeyuki Okada, H. Yamauchi, K. Kawahara, 1995 .

Compensation LSI with WideSearch Range for MPEG2 Video Encoding

Hiroaki Matsuda, Hidenori Satoh, Takumi Watanabe, 1996 .

A 300-MOPS Video Signal Processor With A Parallel Architecture

Toshihiro Minami, Y. Tashiro, Keigo Endo, 1991 .

A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback

Y. Harada, T. Watanabe, H. Yamauchi, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).