Netanel Shavit

Efficiency of Dual Mode Logic in Nanoscale Technology Nodes

Alexander Fish, Ramiro Taco, Netanel Shavit, 2018, 2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE).

Dual Mode Logic Address Decoder

Alexander Fish, Leonid Yavits, Ramiro Taco, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2020, IEEE Solid-State Circuits Letters.

Process Variation-Aware Datapath Employing Dual Mode Logic

Alexander Fish, Ramiro Taco, Netanel Shavit, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology

Alexander Fish, Marco Lanuzza, Leonid Yavits, 2020, ISCAS.

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance

Alexander Fish, Marco Lanuzza, Leonid Yavits, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic

Alexander Fish, Ramiro Taco, Joseph Shor, 2022, IEEE Journal of Solid-State Circuits.

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).