Tim Kerins

发表

FPGA Implementation of a GF(2m) Tate Pairing Architecture

Maurice Keller, Tim Kerins, Francis M. Crowe, 2006, ARC.

Single-chip FPGA implementation of a cryptographic co-processor

Tim Kerins, Francis M. Crowe, William P. Marnane, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve

Tim Kerins, Colin C. Murphy, Colm O'hEigeartaigh, 2007, J. Syst. Archit..

Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes

Tim Kerins, William P. Marnane, Emanuel M. Popovici, 2004, FPL.

Public-Key Cryptography for RFID-Tags

Tim Kerins, Ingrid Verbauwhede, Nele Mentens, 2007, Fifth Annual IEEE International Conference on Pervasive Computing and Communications Workshops (PerComW'07).

A Cautionary Note on Weak Implementations of Block Ciphers

Tim Kerins, Klaus Kursawe, K. Kursawe, 2006 .

Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)

Tim Kerins, William P. Marnane, Emanuel M. Popovici, 2002, FPL.

Table of Contents The International Conference on Information Technology: New Generations (ITNG 2007)

Paulo S. L. M. Barreto, Giovanni Agosta, Gerardo Pelosi, 2007 .

Design for reuse of elliptic curve cryptosystem processors for FPGAs

Tim Kerins, William P. Marnane, Emanuel Popovici, 2004 .

Efficient Hardware for the Tate Pairing Calculation in Characteristic Three

Paulo S. L. M. Barreto, Tim Kerins, William P. Marnane, 2005, CHES.

An Elliptic Curve Processor Suitable For RFID-Tags

Tim Kerins, Ingrid Verbauwhede, Nele Mentens, 2006, IACR Cryptol. ePrint Arch..

Hardware Implementation of the ηT Pairing in Characteristic 3

Tim Kerins, Colin C. Murphy, Colm O'hEigeartaigh, 2006, IACR Cryptol. ePrint Arch..

An FPGA implementation of a GF(p) ALU for encryption processors

Tim Kerins, William P. Marnane, Emanuel M. Popovici, 2004, Microprocess. Microsystems.

A Reconfigurable Processor for the Cryptographic ηT Pairing in Characteristic 3

Tim Kerins, Colin C. Murphy, Colm O'hEigeartaigh, 2007, Fourth International Conference on Information Technology (ITNG'07).

Design of an efficient interface between an FPGA and external memory

Tim Kerins, William P. Marnane, Alan Daly, 2004 .

FPGA acceleration of the tate pairing in characteristic 2

Tim Kerins, Colin C. Murphy, Colm O'hEigeartaigh, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Security in Next Generation Consumer Electronic Devices

Tim Kerins, Klaus Kursawe, Tom Kan, 2006, ISSE.

A flexible processor for the characteristic 3 ηT pairing

Tim Kerins, Robert Ronan, Colin Murphy, 2007, Int. J. High Perform. Syst. Archit..

An Embedded Processor for a Pairing-Based Cryptosystem

Tim Kerins, William P. Marnane, Colin C. Murphy, 2006, Third International Conference on Information Technology: New Generations (ITNG'06).

Fast Modular Division for Application in ECC on Reconfigurable Logic

Tim Kerins, William P. Marnane, Emanuel M. Popovici, 2003, FPL.

A Dedicated Processor for the eta Pairing

Tim Kerins, William P. Marnane, Colin C. Murphy, 2005, IACR Cryptol. ePrint Arch..

Hardware accelerators for pairing based cryptosystems

Paulo S. L. M. Barreto, Tim Kerins, William P. Marnane, 2005 .

Algorithms and architectures for a flexible elliptic curve cryptography processor

Tim Kerins, William P. Marnane, Emanuel Popovici, 2006 .