J. Jussot

Patterning challenges for beyond 3nm logic devices: example of an interconnected magnetic tunnel junction

J. Swerts, S. Couet, N. A. Thiam, 2019, Advanced Lithography.

Line width roughness reduction strategies for patterns exposed via electron beam lithography

L. Pain, Erwine Pargon, B. Icard, 2014, Advanced Lithography.