Il-Hoon Jang

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Ho-Jin Park, Seung-Tak Ryu, Yong-Hee Lee, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

Mi-Young Kim, Jae-Keun Lee, Seung-Tak Ryu, 2017, 2017 Symposium on VLSI Circuits.

An incremental zoom sturdy MASH ADC

Seung-Tak Ryu, Il-Hoon Jang, Ki-Hoon Seo, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

Jae-Keun Lee, Sang-Hyun Cho, Sunwoo Kwon, 2018, IEEE Journal of Solid-State Circuits.

A 1.2㎽ Varible Gain LNA for FM receiver

Sang-Gug Lee, Yang Sun, Il-Hoon Jang, 2012 .

A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

Hyeon-June Kim, Sun-Il Hwang, Seung-Tak Ryu, 2018, IEEE Transactions on Electron Devices.