Marcos Martínez Peiró

Architectures for ICT on FPGA

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Rafael Gadea Gironés, 2004, Microprocess. Microsystems.

2D-DCT on FPGA by polynomial transformation in two-dimensions

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Armando Mora Campos, 2008, Microprocess. Microsystems.

FPGA Custom DSP for ECG Signal Analysis and Compression

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, 2004, FPL.

An active methodology for teaching electronic systems design

Marcos Martínez Peiró, Rafael Gadea Gironés, Ricardo José Colom-Palero, 2006, IEEE Transactions on Education.

2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions

Arturo Méndez Patiño, Marcos Martínez Peiró, 2003, VLSI-SOC.

Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, 2003, FPL.

A new inverse discrete wavelet packet transform architecture

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, 2003, Seventh International Symposium on Signal Processing and Its Applications, 2003. Proceedings..