J. Anderson

发表

Area-efficient FPGA logic elements: Architecture and synthesis

Qiang Wang, Jason Helge Anderson, J. Anderson, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski, 2013, TECS.

The VTR project: architecture and CAD for FPGAs from verilog to routing

Kenneth B. Kent, Jason Luu, Jeffrey B. Goeders, 2012, FPGA '12.

High-Level Synthesis of FPGA Circuits with Multiple Clock Domains

Jason Helge Anderson, Omar Ragheb, Omar Ragheb, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Multi-pumping for resource reduction in FPGA high-level synthesis

Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Active leakage power optimization for FPGAs

Tim Tuan, Jason Helge Anderson, Farid N. Najm, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FPGA-based CNN inference accelerator synthesized from multi-threaded C software

Jason Helge Anderson, John Brothers, Brett Grady, 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

Power Modeling for Heterogeneous Processors

Natalie D. Enright Jerger, Jason Helge Anderson, Tahir Diop, 2014, GPGPU@ASPLOS.

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Yu Ting Chen, Fabrizio Ferrandi, Vlad Mihai Sima, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A PUF design for secure FPGA-based embedded systems

Jason Helge Anderson, J. Anderson, J. Anderson, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski, 2011, FPGA '11.

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Jason Luu, Jason Helge Anderson, Jonathan Rose, 2011, FPGA '11.

Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC

Emanuele Del Sozzo, K. Sano, Omar Ragheb, 2023, HEART.

CGRA-ME: A unified framework for CGRA modelling and exploration

Jason Helge Anderson, Noriaki Sakamoto, Yuko Hara-Azumi, 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

The First 25 Years of the FPL Conference

Marco Platzner, Viktor K. Prasanna, Hideharu Amano, 2017, ACM Trans. Reconfigurable Technol. Syst..

A novel low-power FPGA routing switch

F. Najm, J. Anderson, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Sensei: An area-reduction advisor for FPGA high-level synthesis

Jason Helge Anderson, Hsuan Hsiao, Hsuan Hsiao, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hybrid LUT/Multiplexer FPGA Logic Architectures

Jason Luu, Jason Helge Anderson, S. Alexander Chin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Compact Area and Performance Modelling for CGRA Architecture Evaluation

Jason H. Anderson, Kuang-Ping Niu, Kuang-Ping Niu, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Power Optimization and Prediction Techniques for FPGAs

Jason H. Anderson, J. Anderson, 2005 .

Source-level debugging for FPGA high-level synthesis

Jason Helge Anderson, Stephen Dean Brown, Nazanin Calagar, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Leveraging reconfigurability to raise productivity in FPGA functional debug

Andreas G. Veneris, Zissis Poulos, Jason Helge Anderson, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Area-Driven FPGA Logic Synthesis Using Reinforcement Learning

J. Anderson, Guanglei Zhou, 2023, 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC).

Synthesizable Heterogeneous FPGA Fabrics

Brett Grady, Jason H. Anderson, Brett Grady, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

VTR 7.0: Next Generation Architecture and CAD System for FPGAs

Sen Wang, Kenneth B. Kent, Vaughn Betz, 2014, TRETS.

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code

George A. Constantinides, John Wickerson, Shane T. Fleming, 2022, IEEE Transactions on Computers.

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Jason Helge Anderson, Jin Hee Kim, Jin Hee Kim, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs

Jason Helge Anderson, Brett Grady, Brett Grady, 2019, HEART.

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Jason Helge Anderson, Jin Hee Kim, J. Anderson, 2017, ACM Trans. Reconfigurable Technol. Syst..

Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays

Jason Helge Anderson, Charles Eric LaForest, J. Anderson, 2017, ACM Trans. Reconfigurable Technol. Syst..

On Hard Adders and Carry Chains in FPGAs

Bo Yan, Sen Wang, Kenneth B. Kent, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

Power estimation techniques for FPGAs

Jason Helge Anderson, Farid N. Najm, F. Najm, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Towards interconnect-adaptive packing for FPGAs

Jason Luu, Jason Helge Anderson, Jonathan Rose, 2014, FPGA.

Combined Architecture/Algorithm Approach to Fast FPGA Routing

Marcel Gort, Jason Helge Anderson, Marcel Gort, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reducing FPGA Router Run-Time through Algorithm and Architecture

Marcel Gort, Jason Helge Anderson, Marcel Gort, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Power-aware technology mapping for LUT-based FPGAs

Jason Helge Anderson, Farid N. Najm, F. Najm, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

A Placement Algorithm for FPGA Designs with Multiple I/O Standards

Jason Helge Anderson, Sudip Nag, Jim Saunders, 2000, FPL.

Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010

Marcel Gort, Jason Helge Anderson, Marcel Gort, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration

Jason Helge Anderson, Jongeun Lee, Hyeon Uk Sim, 2019, ASP-DAC.

Leveraging Unused Resources for Energy Optimization of FPGA Interconnect

Jason H. Anderson, Safeen Huda, Safeen Huda, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimizing effective interconnect capacitance for FPGA power reduction

Hirotaka Tamura, Jason Helge Anderson, Safeen Huda, 2014, FPGA.

Charge recycling for power reduction in FPGA interconnect

Hirotaka Tamura, Jason Helge Anderson, Safeen Huda, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.