P. Mohan

Top-down Physical Design of Soft Embedded FPGA Fabrics

Lawrence T. Pileggi, Ken Mai, V. Mohammed Zackriya, 2021, FPGA.

ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS

Jakub Szefer, Prashanth Mohan, Wen Wang, 2020, 2020 IEEE 38th International Conference on Computer Design (ICCD).

Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion

Lawrence T. Pileggi, Ken Mai, Joseph Sweeney, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow

Prashanth Mohan, Ken Mai, Oguz Atli, 2020, FPGA.