David W. Boerstler

On-chip circuit for measuring multi-GHz clock signal waveforms

Keith A. Jenkins, Phillip Restle, P. Z. Wang, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

A new test and characterization scheme for 10+ GHz low jitter wide band PLL

Yuichi Goto, Jieming Qi, David W. Boerstler, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Implementation of the 65nm Cell Broadband Engine

Sang H. Dhong, Osamu Takahashi, Brian K. Flachs, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Design methodology for a 1.0 GHz microprocessor

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

IBM Enterprise Systems multimode fiber optic technology

Daniel J. Stigliani, Frank D. Ferraiolo, David W. Boerstler, 1992, IBM J. Res. Dev..

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Yong Kim, Kevin G. Stawiasz, Keith A. Jenkins, 2015, IEEE Journal of Solid-State Circuits.

"Timing closure by design," a high frequency microprocessor design methodology

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 2000, Proceedings 37th Design Automation Conference.

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology

Kevin J. Nowka, Fadi H. Gebara, Tuyet Nguyen, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor

Kevin G. Stawiasz, Seongwon Kim, Raphael Robertazzi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).