Kobayashi Kazutoshi

发表

A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process

Ebara Mitsunori, Y. Kodai, Furuta Jun, 2018 .

Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes

Ebara Mitsunori, Y. Kodai, Furuta Jun, 2018 .

Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations

Furuta Jun, Kobayashi Kazutoshi, Umehara Shigehiro, 2016 .

Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes.

Sonezaki Eiji, Kanto Kubota, Masuda Masaki, 2015 .

NBTI Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement

Matsumoto Takashi, Kobayashi Kazutoshi, Hosaka Takumi, 2019 .

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element

Onodera Hidetoshi, Furuta Jun, Kobayashi Kazutoshi, 2010 .

Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay

Onodera Hidetoshi, Kobayashi Kazutoshi, Matsumoto Takashi, 2014 .

Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values

Yao Jun, Shimada Hajime, Masuda Masaki, 2013 .

How to Mitigate Reliability-related Issues on Nano-scaled LSIs

Kobayashi Kazutoshi, Kobayashi Kazutoshi, 2012 .

A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets

O. Hidetoshi, Furuta Jun, Kobayashi Kazutoshi, 2011 .