Marcin Rogawski

发表

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2011, CHES.

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs

Kris Gaj, Jens-Peter Kaps, Ekawat Homsirikamol, 2010, 2010 International Conference on Field Programmable Logic and Applications.

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2012, IACR Cryptol. ePrint Arch..

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

Jens-Peter Kaps, Ahmad Salman, Marcin Rogawski, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices

Marcin Rogawski, 2003, IACR Cryptol. ePrint Arch..

Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2010, CHES.

Cryptographic Hardware and Embedded Systems – CHES 2016

Marian Srebrny, Kris Gaj, Pawel Morawiecki, 2016, Lecture Notes in Computer Science.

Development and Benchmarking of New Hardware Architectures for Emerging Cryptographic Transformations

Marcin Rogawski, M. Rogawski, 2013 .

Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates

Kris Gaj, Marcin Rogawski, Rabia Shahid, 2011, 2011 International Conference on Field-Programmable Technology.

A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl

Kris Gaj, Marcin Rogawski, 2012, 2012 15th Euromicro Conference on Digital System Design.

ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption

Marian Srebrny, Marcin Wójcik, Kris Gaj, 2014, IACR Cryptol. ePrint Arch..

Groestl Tweaks and their Effect on FPGA Results

Kris Gaj, Marcin Rogawski, 2011, IACR Cryptol. ePrint Arch..

Security margin evaluation of SHA-3 contest finalists through SAT-based attacks

Marian Srebrny, Pawel Morawiecki, Ekawat Homsirikamol, 2012, IACR Cryptol. ePrint Arch..

Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off

Kris Gaj, Marcin Rogawski, Rabia Shahid, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve

Patrick Baier, Kris Gaj, Soonhak Kwon, 2010, IEEE Transactions on Computers.

A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2013, Microprocess. Microsystems.

Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architectures in Xilinx and Altera FPGAs

Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj George Mason, 2011 .

A High-Speed Unified Hardware Architecture for 128 and 256-bit Security Levels of AES and Grøstl

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, 2013 .

Lessons Learned from Designing a 65 nm ASIC for Evaluating Third Round SHA-3 Candidates

Kris Gaj, Hubert Kaeslin, Frank K. Gürkaynak, 2012 .

Hardware evaluation of eSTREAM Candidates : Grain , Lex , Mickey 128 , Salsa 20 and Trivium

Marcin Rogawski, S. A. Warsaw, 2007 .

Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates

Marcin Rogawski, Malik Umar Sharif, M. Sharif, 2011 .