Pietro Andreani

发表

Time Domain Analysis of Open Loop Distortion in Class D Amplifier Output Stages

Pietro Andreani, Flemming Nyboe, L. Risbo, 2005 .

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO

Pietro Andreani, Luca Fanori, Antonio Liscidini, 2012, 2012 IEEE International Solid-State Circuits Conference.

A Chip for Linearization of RF Power Amplifiers using Predistortion based on a Bit-Parallel Complex Multiplier

Pietro Andreani, Lars Sundstro¨m, 2000 .

A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

Pietro Andreani, Sven Mattisson, Siyu Tan, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

An Analysis of Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar

Pietro Andreani, A. Fard, 2007 .

New Technology-Driven Approaches in the Design of Preamplifiers for Condenser Microphones

Pietro Andreani, Erik Bruun, Pirmin Hermann Otto Rombach, 2009 .

Phase Noise Analysis of the Tuned-Input–Tuned-Output (TITO) Oscillator

Pietro Andreani, Andrea Bevilacqua, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 65 nm CMOS Wideband Radio Receiver With $\Delta \Sigma $-Based A/D-Converting Channel-Select Filters

Xiaodong Liu, Pietro Andreani, Henrik Sjöland, 2016, IEEE Journal of Solid-State Circuits.

A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

Pietro Andreani, Muhammad Shakir, Mohammed Abdulaziz, 2011, 2011 NORCHIP.

Noise optimization of an inductively degenerated CMOS low noise amplifier

Pietro Andreani, Henrik Sjöland, P. Andreani, 2001 .

Still More on the $1/f^{2}$ Phase Noise Performance of Harmonic Oscillators

Pietro Andreani, Federico Pepe, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects

Pietro Andreani, Andrea Bevilacqua, Matteo Bassi, 2020, IEEE Journal of Solid-State Circuits.

A Time-Variant Analysis of Fundamental Phase Noise in CMOS Parallel

Pietro Andreani, Andrea Mazzanti, 2009 .

Highly functional tunnelling devices integrated in 3D

Pietro Andreani, Erik Lind, Lars-Erik Wernersson, 2003, Int. J. Circuit Theory Appl..

A low-power 2nd-order CT delta–sigma modulator with an asynchronous SAR quantizer

Pietro Andreani, Lars Sundström, Dejan Radjen, 2015 .

A digital PLL with a multi-delay coarse-fine TDC

Pietro Andreani, Ping Lu, Ying Wu, 2011, 2011 NORCHIP.

A CMOS current amplifier for biological sensors

Pietro Andreani, Johan Piper, 1998 .

A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

Pietro Andreani, Antonio Liscidini, Ping Lu, 2013 .

A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz

Pietro Andreani, Andrea Mazzanti, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

Pietro Andreani, Andrea Bevilacqua, Matteo Camponeschi, 2011 .

Toroidal inductors in CMOS processes

Pietro Andreani, Rinaldo Castello, Enrico Temporiti, 2005, 2005 NORCHIP.

A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers

Pietro Andreani, Luca Fanori, Antonio Liscidini, 2014, IEEE Journal of Solid-State Circuits.

A 0.2V 0.44uW 20KHz Analog to Digital Sigma Delta Modulator with 57fJ/conversion FoM

Pietro Andreani, Dag T. Wisland, Ulrik Wismar, 2006 .

45% Power Saving in a 0.25/spl mu/m BiCMOS 10Gb/s 50/spl Omega/-Terminated Packaged Active-Load Laser Driver

Pietro Andreani, Emre Ayranci, Kenn Christensen, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 7.5mW 9MHz CT ΔΣ modulator in 65nm CMOS with 69 dB SNDR and reduced sensitivity to loop delay variations

Pietro Andreani, Martin Anderson, Mattias Andersson, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

Characteristic polynomial and zero polynomial with the Cochrun-Grabel method

Pietro Andreani, Sven Mattisson, 1998, Int. J. Circuit Theory Appl..

A 100MHz CMOS g m –C bandpass filter

Pietro Andreani, Sven Mattisson, 1999 .

A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs

Pietro Andreani, Antonio Liscidini, Ping Lu, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback

Pietro Andreani, Lars Sundström, Dejan Radjen, 2011, 2011 NORCHIP.

Serendipitous noise reduction in inductively degenerated CMOS RF LNAs

Pietro Andreani, Francesco Svelto, Paolo Giorgi Rossi, 2003 .

Analysis and design of a low-power single-stage CMOS wireless receiver

Pietro Andreani, Andrea Bevilacqua, Matteo Camponeschi, 2009, 2009 NORCHIP.

A toroidal inductor integrated in a standard CMOS process

Pietro Andreani, Rinaldo Castello, Enrico Temporiti, 2007 .

Comparison of the image rejection between the passive and the Gilbert mixer

Pietro Andreani, Xiaoyan Wang, P. Andreani, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Report on the ESO Workshop ''The Impact of Herschel Surveys on ALMA Early Science''

Pietro Andreani, Goran L. Pilbratt, Leonardo Testi, 2011 .

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Pietro Andreani, Roberto Roncella, Roberto Saletti, 1999 .

A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier

Pietro Andreani, Lars Sundström, Martin Anderson, 2013, 2013 NORCHIP.

A Filtering ΔΣ ADC for LTE and Beyond

Pietro Andreani, Sven Mattisson, Lars Sundström, 2014, IEEE Journal of Solid-State Circuits.

A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier

Pietro Andreani, Niklas Karlsson, Lars Sundström, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor

Pietro Andreani, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Multihit multichannel time-to-digital converter with /spl plusmn/1% differential nonlinearity and near optimal time resolution

Pietro Andreani, Roberto Roncella, Roberto Saletti, 1998 .

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

Pietro Andreani, Ping Lu, Ying Wu, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

On the use of Nauta's transconductor in low-frequency CMOS g/sub m/-C bandpass filters

Pietro Andreani, Sven Mattisson, 2002 .

More on the Phase Noise Performance of CMOS

Pietro Andreani, A. Fard, 2006 .

A 2GHz Low-Phase-Noise CMOS quadrature VCO

Pietro Andreani, Xiaoyan Wang, 2002 .

An Analysis of $1/f$ Noise to Phase Noise Conversion in CMOS Harmonic Oscillators

Pietro Andreani, Andrea Bevilacqua, P. Andreani, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-phase-noise 3.4–4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz

Pietro Andreani, Luca Fanori, P. Andreani, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

Class-D CMOS Oscillators

Pietro Andreani, Luca Fanori, P. Andreani, 2013, IEEE Journal of Solid-State Circuits.

Analysis and Design of a 1.8-GHz CMOS LC

Pietro Andreani, Carlo Samori, Andrea Bonfanti, 2002 .

Phase noise reduction in RF CMOS VCO's via capacitive filtering

Pietro Andreani, 2001 .

New Associate Editors

Pietro Andreani, Michael P. Flynn, SeongHwan Cho, 2016, IEEE J. Solid State Circuits.

Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs

Pietro Andreani, Xiaoyan Wang, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

A 2.5-to-3.3GHz CMOS Class-D VCO

Pietro Andreani, Luca Fanori, P. Andreani, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Design of CMOS Sigma-Delta modulators for audio applications

Pietro Andreani, Erik Bruun, Shen Qifeng, 2007 .

A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer

Pietro Andreani, Lars Sundström, Martin Anderson, 2014, 2014 NORCHIP.

On the Remarkable Performance of the Series-Resonance CMOS Oscillator

Pietro Andreani, Andrea Bevilacqua, Federico Pepe, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Accurate Analysis of Phase Noise in CMOS Ring Oscillators

Pietro Andreani, Federico Pepe, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

Pietro Andreani, Luca Fanori, P. Andreani, 2013, IEEE Journal of Solid-State Circuits.

A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs

Pietro Andreani, Sven Mattisson, Siyu Tan, 2020, 2020 IEEE Nordic Circuits and Systems Conference (NorCAS).

Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO

Pietro Andreani, Andrea Bevilacqua, Marc Tiebout, 2020, IEEE Journal of Solid-State Circuits.

Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators

Pietro Andreani, Lars Sundström, Mattias Andersson, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers

Pietro Andreani, Luca Fanori, Antonio Liscidini, 2012, 2012 IEEE International Solid-State Circuits Conference.

Custom DSP implementation of a GSM speech coder

Pietro Andreani, Viktor Öwall, Peter Nilsson, 1993 .

A 0.6–3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters

Xiaodong Liu, Pietro Andreani, Henrik Sjöland, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A transmitter CMOS VCO for WCDMA/EDGE

Pietro Andreani, Kirill Kozmin, Thomas Mattsson, 2010, 2010 Proceedings of ESSCIRC.

A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping

Pietro Andreani, Ping Lu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Pietro Andreani, Antonio Liscidini, Ping Lu, 2012, IEEE Journal of Solid-State Circuits.

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Pietro Andreani, Andrea Mazzanti, Francesco Svelto, 2004 .

Digital background calibration in continuous-time delta-sigma analog to digital converters

Pietro Andreani, Mattias Palm, Yun Miao, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process

Pietro Andreani, Luca Fanori, Thomas Mattsson, 2016 .

A Time-Variant Analysis of Fundamental $1/f^{3}$ Phase Noise in CMOS Parallel $LC$ -Tank Quadrature Oscillators

Pietro Andreani, Andrea Mazzanti, P. Andreani, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

Pietro Andreani, Nikolaus Klemmer, Satish Uppathil, 2011, 2011 IEEE International Solid-State Circuits Conference.

A General Theory of Phase Noise in Transconductor-Based Harmonic Oscillators

Pietro Andreani, Federico Pepe, P. Andreani, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Integrated circuits for multimedia applications

Pietro Andreani, Luca Vandi, P. Andreani, 2007 .

A compact CMOS MEMS microphone with 66dB SNR

Pietro Andreani, Pirmin Rombach, Erik Bruun, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

Pietro Andreani, Lars Sundström, Dejan Radjen, 2013 .

Reactors - Circuit Theory and Silicon Integrated Applications

Pietro Andreani, 1999 .

A mixed mode design flow for multi GHz ADPLLs

Pietro Andreani, Muhammad Shakir, Mohammed Abdulaziz, 2011, 2011 NORCHIP.

A 1.8-GHz CMOS VCO tuned by an accumulation-mode MOS varactor

Pietro Andreani, Sven Mattisson, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A 2.4-GHz CMOS monolithic VCO based on an MOS varactor

Pietro Andreani, Sven Mattisson, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A 2.7–6.1GHz CMOS local oscillator based on frequency multiplication by 3/2

Pietro Andreani, Andrea Bevilacqua, 2011, 2011 NORCHIP.

Circuits and devices with integrated VFETs and RTDs

Pietro Andreani, Erik Lind, Lars-Erik Wernersson, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A TX VCO for WCDMA/EDGE in 90 nm RF CMOS

Pietro Andreani, Magnus Nilsson, Kirill Kozmin, 2011, IEEE Journal of Solid-State Circuits.

On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory

Pietro Andreani, Andrea Bevilacqua, P. Andreani, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Impact of MOS threshold-voltage mismatch in current-steering DACs for CT delta-sigma modulators

Pietro Andreani, Mattias Andersson, Lars Sundström, 2010, ISCAS 2010.

A Parasitic Insensitive Transconductance-C Bandpass Filter

Pietro Andreani, 1998 .

A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration

Pietro Andreani, Mattias Palm, Roland Strandberg, 2020, ISCAS.

Lessons from ten years of the international master's program in System-on-Chip

Pietro Andreani, Krzysztof Kuchcinski, Lars-Erik Wernersson, 2014, 10th European Workshop on Microelectronics Education (EWME).

Dynamic bias schemes for class-C VCOs

Pietro Andreani, Luca Fanori, 2011, 2011 NORCHIP.

A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

Pietro Andreani, Ahmed Mahmoud, Ping Lu, 2016 .

A GSM speech coder implemented on a customized processor architecture

Pietro Andreani, Viktor Öwall, Peter Nilsson, 1993, 1993 IEEE International Symposium on Circuits and Systems.

SNR in 90 nm CMOS

Pietro Andreani, Dag T. Wisland, Ulrik Wismar, 2007 .

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Pietro Andreani, Ahmed Mahmoud, Ping Lu, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS

Xiaodong Liu, Pietro Andreani, Lars Sundström, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression

Pietro Andreani, Sven Mattisson, Martin Anderson, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

An experimental comparison between two widely adopted phase noise models

Pietro Andreani, Federico Pepe, 2016, 2016 IEEE Nordic Circuits and Systems Conference (NORCAS).

A 2.8–3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS

Pietro Andreani, Federico Pepe, Ahmed Mahmoud, 2017, IEEE Microwave and Wireless Components Letters.

Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end

Pietro Andreani, Andrea Bevilacqua, Andrea Neviani, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches

Pietro Andreani, Tobias Tired, 2011, 2011 NORCHIP.

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion

Pietro Andreani, Andrea Bevilacqua, Matteo Bassi, 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils

Pietro Andreani, Luca Fanori, Thomas Mattsson, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A Push–Pull Class-C CMOS VCO

Pietro Andreani, Andrea Mazzanti, P. Andreani, 2013, IEEE Journal of Solid-State Circuits.

Spectrum Emission Considerations for

Pietro Andreani, Lars Sundström, Roland Strandberg, 2005 .

Distortion and error reduction in a class D power stage using feedback

Pietro Andreani, K. S. Chao, Michael Pate, 2005 .

Bandwidth considerations for a CALLUM transmitter architecture

Pietro Andreani, Lars Sundström, R. Strandberg, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing

Pietro Andreani, Ronan A. R. van der Zee, Dawei Ye, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process

Pietro Andreani, Luca Fanori, Thomas Mattsson, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 2GHz, 17% tuning range quadrature CMOS VCO with high figure–of–merit and 0.6° phase error

Pietro Andreani, 2002 .

A 57-dB image band rejection CMOS G/sub m/-C polyphase filter with automatic frequency tuning for Bluetooth

Pietro Andreani, Weiyun Shan, Bo Shi, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

Pietro Andreani, Lars Sundström, Martin Anderson, 2014 .

A Class-D CMOS DCO with an on-chip LDO

Pietro Andreani, Luca Fanori, Thomas Mattsson, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

Chip for wideband digital predistortion RF power amplifier linearisation

Pietro Andreani, Lars Sundström, 1997 .

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Pietro Andreani, Ping Lu, Ying Wu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Technology scaling impact on embedded ADC design for telecom receivers

Pietro Andreani, Andrea Baschirotto, Piero Malcovati, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

Pietro Andreani, Andrea Bevilacqua, 2011 .

A CMOS g/sub m/-C IF filter for Bluetooth

Pietro Andreani, S. Mattisson, P. Andreani, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Pietro Andreani, Francesco Svelto, Andrea Mazzanti, 2005 .

Low power multi-band CMOS receiver front-end

Pietro Andreani, Henrik Sjoland, Kittichai Phansathitwong, 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics.

A high-swing complementary class-C VCO

Pietro Andreani, Luca Fanori, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

Tail current noise suppression in RF CMOS VCOs

Pietro Andreani, Henrik Sjöland, P. Andreani, 2002, IEEE J. Solid State Circuits.

Characteristic polynomial and zero polynomial with the Cochrun-Grabel method

Pietro Andreani, Sven Mattisson, P. Andreani, 1998, International journal of circuit theory and applications.

Extension of the Cochrun-Grabel method to allow for mutual inductances

Pietro Andreani, Sven Mattisson, P. Andreani, 1999 .

Very low phase noise RF quadrature oscillator architecture

Pietro Andreani, 2001 .

A switched-transformer, 76% tuning-range VCO in 90nm CMOS

Pietro Andreani, Yiming Huo, Thomas Mattsson, 2010, 2010 Asia-Pacific Microwave Conference.