Aditya Jagirdar

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2008, 21st International Conference on VLSI Design (VLSID 2008).

A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Novel flip-flop designs tolerant to soft-errors and crosstalk effects

Aditya Jagirdar, Aditya Jagirdar, 2007 .

Efficient Flip-Flop Designs for SET / SEU Mitigation with Tolerance to Crosstalk Induced Signal Delays

Aditya Jagirdar, Roystein Oliveira, Aditya Jagirdar, 2007 .