Hidekazu Terai

发表

A Routing Procedure for Mixed Array of Custom Macros and Standard Cells

Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa, 1985, 22nd ACM/IEEE Design Automation Conference.

Co-evolutionary robotics using two kinds of neural networks

Hidekazu Terai, Masaya Yoshikawa, 2006, CAINE.

Design of Dedicated Hardware for Ant Colony Optimaization

Hidekazu Terai, Masaya Yoshikawa, Naoyuki Ishiyama, 2008 .

Hardware‐oriented ant colony optimization and its application to dynamic route guidance problem

Hidekazu Terai, Masaya Yoshikawa, 2011 .

Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's

Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, 1986, DAC 1986.

Scalable GA processor architecture and its implementation of processor-element

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Architecture for High Speed Evolutionary Computation

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2003 .

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2008, IEEE Games Entertainment Media Conference.

Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption

Hidekazu Terai, Masaya Yoshikawa, 2007, J. Adv. Comput. Intell. Intell. Informatics.

Performance‐driven placement procedure for low power

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

Asynchronous parallel genetic algorithm for congestion-driven placement technique

Hidekazu Terai, Masaya Yoshikawa, 2005, Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05).

Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's

Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, 1986, 23rd ACM/IEEE Design Automation Conference.

VLSI processor architecture for real-time GA processing and PE-VLSI design

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

免疫アルゴリズムをベースとするＮＳＰ専用エンジンアーキテクチャとその評価;免疫アルゴリズムをベースとするＮＳＰ専用エンジンアーキテクチャとその評価;Immune Algorithm Processor for Nurse Scheduling Problem

Hidekazu Terai, Malaya Yoshikawa, 2006 .

Architecture for high‐speed evolutionary computation

Hidekazu Terai, Masaya Yoshikawa, Tetsuya Imai, 2004 .

The new DFM approach based on a genetic algorithm

Hidekazu Terai, Masaya Yoshikawa, 2006, Artificial Life and Robotics.

Dedicated hardware for inheritance-oriented crossover operation

Hidekazu Terai, Masaya Yoshikawa, Kentaro Otsuka, 2008 .

A Description of Chinese Characters Using Sub-patterns

Makoto Nagao, Hidekazu Terai, Toshiyuki Sakai, 1969 .

Congestion-Driven Parallel Placement Procedure for LSI Cells Based on Hybrid Genetic Algorithm

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2001 .

Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1

Hidekazu Terai, Yasuo Satoh, Yasuhiro Ohno, 1994, 31st Design Automation Conference.

LSI Cell Parallel Placement Technique Based on Genetic Algorithms

Hidekazu Terai, Masaya Yoshikawa, 2000 .

Q-learning based on hierarchical evolutionary mechanism

Hidekazu Terai, Masaya Yoshikawa, Takeshi Kihira, 2008 .

A hierarchical parallel placement technique based on genetic algorithm

Hidekazu Terai, Masaya Yoshikawa, 2005, 5th International Conference on Intelligent Systems Design and Applications (ISDA'05).

A novel timing-driven placement using genetic algorithm

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2003, Southwest Symposium on Mixed-Signal Design, 2003..

Combine and Top Down Block Placement Algorithm for Hierarchical Logic VLSI Layout

Hidekazu Terai, Tokinori Kozawa, Chihei Miura, 1984, 21st Design Automation Conference Proceedings.

Dedicated Hardware for Ant Colony Optimization Using Distributed Memory

Hidekazu Terai, Masaya Yoshikawa, 2009, 2009 Sixth International Conference on Information Technology: New Generations.

Routing Procedure and Job Assignment Algorithm for VLSI Chip Design on a Parallel Computer

Hidekazu Terai, Tomonari Sakagami, 智成坂上, 1997 .

Automatic Placement Algorithms for High Packing density VLSI

Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa, 1983, 20th Design Automation Conference Proceedings.

Dedicated Hardware for Hybrid Evolutionary Computation

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2009 .

Hierarchical Automatic Layout Algorithms for Custom Logic LSI

Hidekazu Terai, 1988 .

Architecture for High Speed Learning of Neural Network using Genetic Algorithm

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

A Routing Procedure for Mixed Array of Custom Macros and Standard Cells

Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa, 1985, DAC 1985.

Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation

Hidekazu Terai, Masaya Yoshikawa, 2006, J. Adv. Comput. Intell. Intell. Informatics.

Basic concepts of timing-oriented design automation for high-performance mainframe computers

Hidekazu Terai, Tokinori Kozawa, Fumio Goto, 1991, 28th ACM/IEEE Design Automation Conference.

Channel Routing Technique Based on Genetic Algorithms for Minimum Crosstalk

Hidekazu Terai, Masaya Yoshikawa, 2001 .

Performance Driven Placement Procedure for Low Power

Hidekazu Terai, Masaya Yoshikawa, 2004 .

Genetic learning using adaptive action value tables

Hidekazu Terai, Masaya Yoshikawa, Takeshi Kihira, 2008 .

Timing-Driven Placement Technique based on Evolutionary method

Hidekazu Terai, Masaya Yoshikawa, Tomohiro Fujita, 2002 .

Performance driven placement technique based on collaboration of software and hardware

Hidekazu Terai, Masaya Yoshikawa, 2005, 2005 IEEE Congress on Evolutionary Computation.

Genetic-based machine learning using hardware accelerator

Hidekazu Terai, Masaya Yoshikawa, 2008 .

C-007 Genetic Algorithm Engine for VLSI Floorplanning

Hidekazu Terai, Masaya Yoshikawa, Akihiro Maeda, 2007 .

Automatic Layout Design Method for Full Custom VLSI

Hidekazu Terai, Tokinori Kozawa, Yoshinori Sakataya, 1985 .

AND ITS IMPLEMENTATION OF PROCESSOR-ELEMEN T

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2002 .

Route selection algorithm based on integer operation Ant Colony Optimization

Hidekazu Terai, Masaya Yoshikawa, 2008, IRI.

Hybrid Architecture of Genetic Algorithm and Simulated Annealing

Hironori Yamauchi, Hidekazu Terai, Masaya Yoshikawa, 2008, Eng. Lett..

A GA-based Floorplanning method for Topological Constraint

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

Crossover operation engine considering character inheritance

Hidekazu Terai, Masaya Yoshikawa, Kentaro Otsuka, 2008 .

OX Hardware Engine for High Speed Character Inheritance

Hidekazu Terai, Masaya Yoshikawa, 2009, GEM.

A new genetic coding for job shop scheduling problem considering geno type and pheno type

Hidekazu Terai, Masaya Yoshikawa, Hideto Nishimura, 2010 .

Apriori, Association Rules, Data Mining,Frequent Itemsets Mining (FIM), Parallel Computing

Hidekazu Terai, Masaya Yoshikawa, 2006, Fourth International Conference on Software Engineering Research, Management and Applications (SERA'06).

Automatic layout procedures for serial routing devices

Hidekazu Terai, Tokinori Kozawa, Yasushi Ogawa, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Architecture for high-speed Ant Colony Optimization

Hidekazu Terai, Masaya Yoshikawa, 2007, 2007 IEEE International Conference on Information Reuse and Integration.

Hardware accelerator for evolutionary robotics

Hidekazu Terai, Masaya Yoshikawa, 2008 .

Parallel Placement Procedure based on Distributed Genetic Algorithms

Takeshi Fujino, Hidekazu Terai, Masaya Yoshikawa, 2005 .

LSI Cell Parallel Placement Technique Based on Evolutionary Method

Hidekazu Terai, Masaya Yoshikawa, 1999 .

Dedicated hardware for scheduling problems using genetic algorithm

Hidekazu Terai, Masaya Yoshikawa, 2006 .

Immune Algorithm Processor

Masahiro Fukui, Hidekazu Terai, Masaya Yoshikawa, 2006, Computers and Their Applications.

Constraint-driven floorplanning based on genetic algorithm

Hidekazu Terai, Masaya Yoshikawa, 2007 .

Car Navigation System Based on Hybrid Genetic Algorithm

Hidekazu Terai, Masaya Yoshikawa, 2009, 2009 WRI World Congress on Computer Science and Information Engineering.

Research in Design Automation for VLSI Layout

Hidekazu Terai, Tokinori Kozawa, H. Terai, 1985, IEEE Design & Test of Computers.