Jihoon Kim

A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

Hoi-Jun Yoo, Wooyoung Jo, Juhyoung Lee, 2021, 2021 Symposium on VLSI Circuits.

A 1.02-μW STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit

Hongsik Jeong, Hoi-Jun Yoo, Changhyeon Kim, 2020, IEEE Solid-State Circuits Letters.

A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error

Hoi-Jun Yoo, Minseo Kim, Surin Gweon, 2020, IEEE Journal of Solid-State Circuits.

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks

Juhyoung Lee, Jinsu Lee, Ji-Hoon Kim, 2021, IEEE Journal of Solid-State Circuits.

22.3 A 0.5V 9.26μW 15.28mΩ/√Hz Bio-Impedance Sensor IC With 0.55° Overall Phase Error

Hoi-Jun Yoo, Ji-Hoon Kim, Yongsu Lee, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 0.8-V 82.9- $\mu$ W In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver

Hoi-Jun Yoo, Unsoo Ha, Jaehyuk Lee, 2019, IEEE Journal of Solid-State Circuits.

OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer

H. Yoo, Donghyeon Han, Sangyeob Kim, 2022, IEEE Journal of Solid-State Circuits.