Yongmi Kim

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

Yunsaing Kim, Jaemin Jang, Hyungsoo Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Hankyu Chi, Dongkyun Kim, Changhyun Lee, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Dongkyun Kim, Minsu Park, Mingyu Park, 2020, IEEE Journal of Solid-State Circuits.