M. Morino

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

H. Fujisawa, S. Narui, S. Miyatake, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 29 ns 64 Mb DRAM with hierarchical array architecture

T. Takahashi, M. Morino, K. Komatsuzaki, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

T. Sekiguchi, M. Nakamura, Y. Ohji, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).