Wonil Bae

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Young Choi, Jung-Hwan Choi, Jongeun Lee, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Jang-Rae Kim, Kihan Kim, Jong-Min Bang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Nam Sung Kim, Chang-Kyo Lee, Hyung-Joon Chi, 2021, IEEE Journal of Solid-State Circuits.