C. Wolf

Malicious LUT: A stealthy FPGA Trojan injected and triggered by the design flow

Axel Jantsch, Christian Krieg, Clifford Wolf, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Yosys-A Free Verilog Synthesis Suite

Johann Glaser, Clifford Wolf, Johannes Kepler, 2013 .

Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic

Jan Haase, Christoph Grimm, Johann Glaser, 2012, Proceeding of the 2012 Forum on Specification and Design Languages.

Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures

Johann Glaser, Clifford Wolf, C. Wolf, 2012, FDL.

Btor2 , BtorMC and Boolector 3.0

Armin Biere, Aina Niemetz, Mathias Preiner, 2018, CAV.

Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs

Eddie Hung, David Shah, Clifford Wolf, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Btor2 , BtorMC and Boolector 3.0

Armin Biere, Aina Niemetz, Mathias Preiner, 2018, CAV.