Jochen Mades

A discrete algorithm for the regularization of hierarchical VHDL-AMS models

Manfred Glesner, Jochen Mades, D. E. Schwarz, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A scalable multithreaded compiler front-end

Wolfgang Ecker, Ke Yang, André Windisch, 2000, PARCO.

An open VHDL-AMS simulation framework

Manfred Glesner, Wolfgang Ecker, André Windisch, 2000, Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation.

Strukturelle Konsistenz und Regularisierung von VHDL-AMS-Modellen

Jochen Mades, 2003 .

Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design)

Manfred Glesner, Wolfgang Ecker, Dieter Monjau, 2000, Informationstechnik Tech. Inform..

Concept of a joint university/industry course for mixed-signal system-on-chip design

Jürgen Becker, Manfred Glesner, Thomas Hollstein, 2001, Proceedings 2001 International Conference on Microelectronic Systems Education.

Regularization of hierarchical VHDL-AMS models using bipartite graphs

Manfred Glesner, Jochen Mades, 2002, DAC '02.

VXML: VHDL Hardware Design Representation in XML

Wolfgang Ecker, Ke Yang, André Windisch, 2000, MBMV.