Soumitra Bose

发表

Path delay fault simulation of sequential circuits

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Delay fault simulation with bounded gate delay mode

Soumitra Bose, Vishwani D. Agrawal, Hillary Grimes, 2007, 2007 IEEE International Test Conference.

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis

Soumitra Bose, Vishwani D. Agrawal, 2007, 2007 IEEE International Test Conference.

Parthenon: A parallel theorem prover for non-horn clauses

Soumitra Bose, Edmund M. Clarke, David E. Long, 2004, Journal of Automated Reasoning.

Generation of compact delay tests by multiple path activation

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1993, Proceedings of IEEE International Test Conference - (ITC).

Upper bounding fault coverage by structural analysis and signal monitoring

Soumitra Bose, Vishwani D. Agrawal, Vijay Gangaram, 2006, 24th IEEE VLSI Test Symposium.

Extraction of schematic array models for memory circuits

Soumitra Bose, Amit Nandi, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Sequential logic path delay test generation by symbolic analysis

Soumitra Bose, Vishwani D. Agrawal, 1995, Proceedings of the Fourth Asian Test Symposium.

Schematic array models for associative and non-associative memory circuits

Soumitra Bose, Amit Nandi, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A rated-clock test method for path delay faults

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1998, IEEE Trans. Very Large Scale Integr. Syst..

The optimistic update theorem for path delay testing in sequential circuits

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1993, J. Electron. Test..

Automated modeling of custom digital circuits for test

Soumitra Bose, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers

Soumitra Bose, Prathima Agrawal, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Concurrent fault simulation on message passing multicomputers

Soumitra Bose, Prathima Agrawal, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Delay fault testability evaluation through timing simulation

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1993, [1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems.

Deriving Logic Systems for Path Delay Test Generation

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, 1998, IEEE Trans. Computers.

Parthenon: A parallel theorem prover for non-horn clauses

Soumitra Bose, Edmund M. Clarke, Spiro Michaylov, 1988, [1989] Proceedings. Fourth Annual Symposium on Logic in Computer Science.

Fault Coverage Estimation for Non-Random Functional Input Sequences

Soumitra Bose, Vishwani D. Agrawal, 2006, 2006 IEEE International Test Conference.

Algorithms for switch level delay fault simulation

Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski, 1997, Proceedings International Test Conference 1997.

Delay Test Quality Evaluation Using Bounded Gate Delays

Soumitra Bose, Vishwani D. Agrawal, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

PARTHENON: a parallel theorem prover for nonHorn clauses

Soumitra Bose, Edmund M. Clarke, David E. Long, 1989, [1989] Proceedings. Fourth Annual Symposium on Logic in Computer Science.

Modeling Custom Digital Circuits for Test

Soumitra Bose, 2004, J. Electron. Test..

Testing for path delay faults in synchronous digital circuits

Soumitra Bose, 1996 .