Ismet Bayraktaroglu

发表

Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test

Yiorgos Makris, Alex Orailoglu, Ismet Bayraktaroglu, 2004, IEEE Transactions on Reliability.

Seamless test of digital components in mixed-signal paths

Sule Ozev, Alex Orailoglu, Ismet Bayraktaroglu, 2004, IEEE Design & Test of Computers.

ANNSyS (an analog neural network synthesis system)

Sina Balkir, Ethem Alpaydin, Ismet Bayraktaroglu, 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues

Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins, 2006, 2006 IEEE International Test Conference.

Instruction based bist for board/system level test of external memories and internconnects

Richard Lee, Ismet Bayraktaroglu, John Bell, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Reducing Average and Peak Test Power Through Scan Chain Modification

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2003, J. Electron. Test..

Gate level fault diagnosis in scan-based BIST

Alex Orailoglu, Ismet Bayraktaroglu, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Selecting a PRPG: randomness, primitiveness, or sheer luck?

Alex Orailoglu, Ismet Bayraktaroglu, 2001, Proceedings 10th Asian Test Symposium.

Test volume and application time reduction through scan chain concealment

Alex Orailoglu, Ismet Bayraktaroglu, A. Orailoglu, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Cost effective digital filter design for concurrent test

Alex Orailoglu, Ismet Bayraktaroglu, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

Alex Orailoglu, Ismet Bayraktaroglu, 2003, IEEE Trans. Computers.

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Alex Orailoglu, Ismet Bayraktaroglu, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Accumulation-based concurrent fault detection for linear digital state variable systems

Alex Orailoglu, Ismet Bayraktaroglu, 2000, Proceedings of the Ninth Asian Test Symposium.

Microprocessor silicon debug based on failure propagation tracing

Ismet Bayraktaroglu, Peter Dahlgren, Olivier Caty, 2005, IEEE International Conference on Test, 2005..

ANNSyS: an Analog Neural Network Synthesis System

Sina Balkir, Günhan Dündar, Ethem Alpaydin, 1999, Neural Networks.

Deterministic partitioning techniques for fault diagnosis in scan-based BIST

Alex Orailoglu, Ismet Bayraktaroglu, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Test power reduction through minimization of scan chain transitions

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: mathematical foundations and cost-effective implementations

Alex Orailoglu, Ismet Bayraktaroglu, 2005, IEEE Transactions on Computers.

Concurrent test for digital linear systems

Alex Orailoglu, Ismet Bayraktaroglu, A. Orailoglu, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test application time and volume compression through seed overlapping

Wenjing Rao, Alex Orailoglu, Ismet Bayraktaroglu, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST

Alex Orailoglu, Ismet Bayraktaroglu, 2002, IEEE Des. Test Comput..

Improved fault diagnosis in scan-based BIST via superposition

Alex Orailoglu, Ismet Bayraktaroglu, 2000, Proceedings 37th Design Automation Conference.

Highly configurable programmable built-in self test architecture for high-speed memories

Ismet Bayraktaroglu, Olivier Caty, Yickkei Wong, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Invariance-based on-line test for RTL controller-datapath circuits

Yiorgos Makris, Alex Orailoglu, Ismet Bayraktaroglu, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Scan power reduction through test data transition frequency analysis

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2002, Proceedings. International Test Conference.

Diagnosis for scan-based BIST: reaching deep into the signatures

Alex Orailoglu, Ismet Bayraktaroglu, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Test synthesis for mixed-signal SOC paths

Sule Ozev, Alex Orailoglu, Ismet Bayraktaroglu, 2000, DATE '00.

An examination of PRPG selection approaches for large, industrial designs

Alex Orailoglu, Ismet Bayraktaroglu, K. Udawatta, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Low-cost on-line test for digital filters

Alex Orailoglu, Ismet Bayraktaroglu, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Combined On-Line / Off-Line Test Solutions for Digital Filters

Alex Orailoglu, Ismet Bayraktaroglu, 1999 .