Masaru Yamamoto

Some Easily Testable and Diagnosable Network Realizations

Takayuki Nakajima, Masaru Yamamoto, Yutaka Ashida, 1976 .

A Method for Minimizing Incompletely Specified Sequential Machines

Masaru Yamamoto, 1980, IEEE Transactions on Computers.

An Information System Model with Two Processing Units

Masaru Yamamoto, Hitoshi Yokoi, 1975 .

Synthesis of fault diagnosable logical circuits

Masaru Yamamoto, 1973 .