C. Diorio

发表

A 2.92μW Hardware Random Number Generator

J. Holleman, B. Otis, S. Bridges, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A 5.5 GHz fractional frequency-synthesizer IC

M. Kintis, C. Diorio, A. Oki, 1997, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997.

A reconfigurable VLSI learning array

S. Bridges, C. Diorio, M. Figueroa, 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

Prolog to adaptive CMOS: from biological inspiration to systems-on-a-chip

C. Diorio, R. O'Donnell, D. Hsu, 2002 .

A miniature implantable computer for functional electrical stimulation and recording of neuromuscular activity

C. Diorio, J. Mavoori, B. Millard, 2004, IEEE International Workshop on Biomedical Circuits and Systems, 2004..

A simulation model for floating-gate MOS synapse transistors

C. Diorio, C. Hernandez, K. Rahimi, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

In-circuit self-tuning of clock latencies

C. Diorio, K. Rahimi, 2005, Sixth international symposium on quality electronic design (isqed'05).

A 3 $\mu$W CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation

J. Holleman, S. Bridges, C. Diorio, 2008, IEEE Journal of Solid-State Circuits.

A Random Projection Imager for Visual Pattern Classification in Analog VLSI

J. Holleman, S. Bridges, A. Mitros, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

C. Diorio, M. Figueroa, J. Hyde, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 19.2GOPS, 20mW adaptive FIR filter

S. Bridges, C. Diorio, D. Hsu, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

S. Bridges, C. Diorio, M. Figueroa, 2004, IEEE Journal of Solid-State Circuits.

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

C. Diorio, C.-H. Wang, T. Gilliland, 2004, IEEE Transactions on Device and Materials Reliability.

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

C. Diorio, R. Paulsen, T. Humes, 2005, IEEE Electron Device Letters.

Study of stress-induced leakage current and charge loss of nonvolatile memory cell with 70 /spl Aring/ tunnel oxide using floating-gate integrator technique

Bin Wang, C. Diorio, Yanjun Ma, 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

Adaptation of Current Signals with Floating-Gate Circuits

C. Diorio, A. Pesavento, T. Horiuchi, 1999, Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems.