K. Watanabe

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications

T. Ando, S. Wada, S. Wakahara, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

The effect of substrate materials on holding time degradation in MOS dynamic RAM

H. Iwai, K. Watanabe, H. Nihira, 1982, IEEE Electron Device Letters.

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

M. Belyansky, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

M. Khare, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Two types of 500 V double gate lateral N-ch bipolar-mode MOSFETs in dielectrically isolated p/sup -/ and n/sup -/ silicon islands

T. Ogura, Y. Yamaguchi, A. Nakagawa, 1988, Technical Digest., International Electron Devices Meeting.

A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

T. Hiramoto, T. Ikeda, M. Odaka, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Non-latch-up 1200V 75A bipolar-mode MOSFET with large ASO

M. Kurata, H. Ohashi, A. Nakagawa, 1984, 1984 International Electron Devices Meeting.