A. Srivastava

Impact of gate workfunction on device performance at the 50 nm technology node

Carlton M. Osburn, Ajit K. Srivastava, C. Osburn, 2000 .

Parasitic Resistance Considerations of Using Elevated Source/Drain Technology for Deep Submicron Metal Oxide Semiconductor Field Effect Transistors

N. A. Masnari, C. Osburn, R. Bartholomew, 1998 .

The effect of the elevated source/drain doping profile on performance and reliability of deep submicron MOSFETs

N. A. Masnari, C. Osburn, R. Bartholomew, 1997 .

Sub-Half Micron Elevated SourceDrain NMOSFETS by Low Temperature Selective Epitaxial Deposition

N. A. Masnari, K. Violette, C. Osburn, 1996 .