Hirotsugu Kajihara

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

Ryuichi Fujimoto, Yosuke Ogasawara, Masaomi Iwanaga, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Makoto Arai, Hiroyuki Kobayashi, Atsushi Suzuki, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Folding of logic functions and its application to look up table compaction

Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, 2002, ICCAD 2002.

Folding of logic functions and its application to look up table compaction

Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications

Hirotsugu Kajihara, Yasuo Unekawa, Toshio Fujisawa, 2011, 2011 IEEE Cool Chips XIV.

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS

Ryuichi Fujimoto, Daisuke Miyashita, Kenichi Sami, 2013, IEICE Trans. Electron..

Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications

Shuou Nomura, Hirotsugu Kajihara, Tatsuo Shiozawa, 2021, Proc. VLDB Endow..