Yasuo Unekawa

发表

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

Ryuichi Fujimoto, Yosuke Ogasawara, Masaomi Iwanaga, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

Yasuo Unekawa, Atsushi Kawasumi, Fumihiko Tachibana, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control

Yasuo Unekawa, Chen Kong Teh, Atsushi Suzuki, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Makoto Arai, Hiroyuki Kobayashi, Atsushi Suzuki, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

IEEE802.11a Based Wireless A/V Data Transmission System

Yasuo Unekawa, Takashi Wakutsu, Eiji Kamagata, 2004 .

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation

Yasuo Unekawa, Toshiyuki Yamagishi, Hiroyuki Hara, 2013, IEICE Trans. Electron..

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation

Yasuo Unekawa, Toshiyuki Yamagishi, Hiroyuki Hara, 2012, 2012 IEEE COOL Chips XV.

32b RISC Processor

Tatsuya Higashi, Yasuo Unekawa, T. Saito, 2003 .

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors

Liesbet Van der Perre, Tom Vander Aa, Yasuo Unekawa, 2011, IEEE Micro.

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing

Hiroyuki Kobayashi, Daisuke Miyashita, Yasuo Unekawa, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

h?=-I Data Streaming Cache

Takayasu Sakurai, Yasuo Unekawa, Yukihiro Fujimoto, 1994 .

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver

Yuichi Sato, Ryuichi Fujimoto, Daisuke Miyashita, 2014, 2014 IEEE Radio and Wireless Symposium (RWS).

A 110-MHz/1-Mb synchronous TagRAM

Takayasu Sakurai, Yasuo Unekawa, Yukihiro Fujimoto, 1994 .

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Hiroyuki Kobayashi, Daisuke Miyashita, Yasuo Unekawa, 2014, IEEE Journal of Solid-State Circuits.

Analog signal processing circuit and communication device so

Yasuo Unekawa, Mototsugu Hamada, Minoru Namekata, 2006 .

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

Daisuke Miyashita, Junji Wadatsumi, Konosuke Watanabe, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications

Hirotsugu Kajihara, Yasuo Unekawa, Toshio Fujisawa, 2011, 2011 IEEE Cool Chips XIV.

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor

Liesbet Van der Perre, Tom Vander Aa, Yasuo Unekawa, 2011, 2011 IEEE Cool Chips XIV.

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS

Ryuichi Fujimoto, Daisuke Miyashita, Kenichi Sami, 2013, IEICE Trans. Electron..