Chia-I Chen

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Yen-Ting Lin, Juinn-Dar Huang, Chia-I Chen, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication

Juinn-Dar Huang, Chia-I Chen, Juinn-Dar Huang, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

Jing-Yang Jou, Juinn-Dar Huang, Chia-I Chen, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Architectural exploration of 3D FPGAs towards a better balance between area and delay

Juinn-Dar Huang, Chia-I Chen, Bau-Cheng Lee, 2011, 2011 Design, Automation & Test in Europe.

CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Juinn-Dar Huang, Chia-I Chen, Juinn-Dar Huang, 2009, 2009 Asia and South Pacific Design Automation Conference.