P. Varma

The economics of scan-path design for testability

Prab Varma, Tushar Gheewala, T. Gheewala, 1994, J. Electron. Test..

A structured test re-use methodology for core-based system chips

Prab Varma, Sandeep Bhatia, S. Bhatia, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Test Cycle Count Reduction in a Parallel Scan BIST Environment

Prab Varma, Bechir Ayari, P. Varma, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

A Fast Signature Simulation Tool for Built-In Self-Testing Circuits

Prab Varma, Keith Baker, R. Porter, 1987, 24th ACM/IEEE Design Automation Conference.