Nan-Chi Chou

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Circuit Partitioning for Huge Logic Emulation Systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1994, 31st Design Automation Conference.

Wire Length And Delay Minimization In General Clock Net Routing

Chung-Kuan Cheng, N. Chou, Nan-Chi Chou, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages

Dongsheng Wang, Nan-Chi Chou, Peter Suaris, 2003, PATMOS.

Local ratio cut and set covering partitioning for huge logic emulation systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..