S. Tatapudi

A high performance hybrid wave-pipelined multiplier

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2005, CDES.

A mesochronous pipelining scheme for high-performance digital systems

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

A high-performance low-power mesochronous pipeline architecture for computer systems

José G. Delgado-Frias, S. B. Tatapudi, J. Delgado-Frías, 2006 .

A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

J.G. Delgado-Frias, S.B. Tatapudi, J. Delgado-Frías, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

AMesochronous Pipeline SchemeforHigh Performance LowPowerDigital Systems

Suryanarayana B. Tatapudi, S. Tatapudi, 2006 .