Hyungcheol Shin

发表

Extraction and modeling of gate electrode resistance in rf MOSFETs

Myounggon Kang, In Man Kang, Hyungcheol Shin, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

A digital temperature compensated crystal oscillator using a temperature adaptive capacitor array

Hyungcheol Shin, Minkyu Je, Hoi-Jun Yoo, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Size efficient low‐noise amplifier for 2.4 GHz ISM‐band transceiver

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Transactions on Nanotechnology.

Fundamental trade-off between parasitic resistance and capacitance in a nanowire-FET technology

Myounggon Kang, Hyungcheol Shin, Hyungwoo Ko, 2016 .

16GHz CMOS LNA design without Source degeneration inductor(Functional Devices and Circuits)

Hyungcheol Shin, Hee Sauk Jhon, Seung Il Choi, 2005 .

Programmable virtual source/drain MOSFETs

Hyungcheol Shin, Il Han Park, Chilhee Chung, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

A 5–GHz band I/Q clock generator using a self–calibration technique

Hyungcheol Shin, Hyung Ki Ahn, Joonho Gil, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Hyungcheol Shin, Byung-Gook Park, Jong-Ho Lee, 2012 .

Integrated LC VCO Compatible with Memory Process for Gigahertz Clock Generation

Hyungcheol Shin, Young-Wug Kim, Minseok Choi, 2006, 2006 IEEE International Conference on Semiconductor Electronics.

A 2.4-GHz CMOS LNA with harmonic cancellation and current reuse technique

Hyungcheol Shin, Joonho Gil, Kwyro Lee, 2003 .

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)

Hyungcheol Shin, Byung-Gook Park, Jong-Ho Lee, 2010, SDM.

Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Characteristics of MOSFET with non-overlapped source-drain to gate region

Hyungcheol Shin, Jong-Ho Lee, Hyunjin Lee, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

Investigation of Frequency Dependent Sensitivity of Noise Figure on Device Parameters in 65 nm CMOS

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

A miniaturized low-power wireless remote environmental monitoring system using microfabricated electrochemical sensing electrodes

Hyungcheol Shin, Kwyro Lee, Joonho Gil, 2003, TRANSDUCERS '03. 12th International Conference on Solid-State Sensors, Actuators and Microsystems. Digest of Technical Papers (Cat. No.03TH8664).

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Suppression of Digital Noise Coupling on LNA in 0.13-μm RFCMOS Technology by Global Guard Rings

Hyungcheol Shin, Tae Hyun Oh, Ickhyun Song, 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

A Simple compact model for hot carrier injection phenomenon in 32 nm NAND flash memory device

Myounggon Kang, Hyungcheol Shin, Il Han Park, 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).

Low power size‐efficient CMOS UWB low‐noise amplifier design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2009 .

A Compact and Low-noise Analog Front-end for Capacitive Touch-panel Controller

Hyungcheol Shin, Kwyro Lee, Hongjae Jang, 2012 .

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

A New Analytical Model for Channel Thermal Noise of Deep-submicron RF MOSFETs

Hyungcheol Shin, Jongwook Jeon, Yujo Yun, 2006 .

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

Hyungcheol Shin, Yoon Kim, Byung-Gook Park, 2009, IEICE Trans. Electron..

A 70dB SNR capacitive touch screen panel readout IC using capacitor-less trans-impedance amplifier and coded Orthogonal Frequency-Division Multiple Sensing scheme

Hyungcheol Shin, Kwyro Lee, Hongjae Jang, 2013, 2013 Symposium on VLSI Circuits.

The novel SCR-based ESD protection with low triggering and high holding voltages

Myounggon Kang, Hyungcheol Shin, Ki-Whan Song, 2011, Microelectron. J..

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Myounggon Kang, Hyungcheol Shin, Byung-Gook Park, 2012, IEEE Transactions on Electron Devices.

12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels

Hyungcheol Shin, Kwyro Lee, Hongjae Jang, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

The Analysis of Input Power Matching for CMOS RF Low Noise Amplifier Design

Hyungcheol Shin, Hee Sauk Jhon, Seung Il Choi, 2005 .

Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell

Hyungcheol Shin, Il Han Park, Jong Duk Lee, 2005 .

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

Hyungcheol Shin, Byung-Gook Park, Yoon Kim, 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

A high speed and low power SOL inverter using active body-bias

Hyungcheol Shin, Minkyu Je, Joonho Gil, 1998, ISLPED '98.

A simple technique to measure generation lifetime in partially depleted SOI MOSFETs

Hyungcheol Shin, Marco Racanelli, W. M. Huang, 1997 .

0.7 V supply highly linear subthreshold low-noise amplifier design for 2.4 GHz wireless sensor network applications

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

Ku-band LNA Design in 0.18 ㎛ Logic CMOS Technology

In Man Kang, Hyungcheol Shin, Joonho Gil, 2005 .

Size-Efficient 3 GHZ CMOS LNA

Hyungcheol Shin, Hee-Sauk Jhon, Ickhyun Song, 2007 .

A high speed and low power SOI inverter using active body-bias

Hyungcheol Shin, Minkyu Je, Joonho Gil, 1999 .

2.4 GHz ISM-Band Receiver Design in a 0.18 $\mu{\hbox{m}}$ Mixed Signal CMOS Process

In Man Kang, Hyungcheol Shin, Hee-Sauk Jhon, 2007, IEEE Microwave and Wireless Components Letters.

Extraction of Substrate Resistance Parameters for RF MOSFETs Based on Three-Port Measurement

In Man Kang, Hyungcheol Shin, 2005 .

A simple wide-band on-chip inductor model for silicon-based RF ICs

Hyungcheol Shin, Joonho Gil, 2003 .

A new RF model for the accumulation-mode MOS varactor

Hyungcheol Shin, Seong-Sik Song, 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

A New Substrate Resistance Model of RF MOSFETs

Hyungcheol Shin, Jong Duk Lee, Youngchang Yoon, 2006 .

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2010, IEEE Transactions on Nanotechnology.

A simple and accurate method for extracting substrate resistance of RF MOSFETs

Hyungcheol Shin, Minkyu Je, Jeonghu Han, 2002 .

A -119.2 dBc/Hz at 1 MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors

Hyungcheol Shin, Joonho Gil, Seong-Sik Song, 2003 .

24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008, SDM 2008.

Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability

Myounggon Kang, Hyungcheol Shin, Dokyun Son, 2017 .

Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices

Myounggon Kang, Hyungcheol Shin, Min-Soo Kim, 2017 .

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Characterization of the Variable Retention Time in Dynamic Random Access Memory

Hyungcheol Shin, Byoungchan Oh, Younghwan Son, 2011, IEEE Transactions on Electron Devices.

A simple and analytical parameter-extraction method of a microwave MOSFET

Hyungcheol Shin, Minkyu Je, Kwyro Lee, 2002 .

Low noise capacitive sensor for multi-touch mobile handset's applications

Hyungcheol Shin, Kwyro Lee, Jaemin Lee, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

CMOS RF modeling and parameter extraction approaches taking charge conservation into account

Hyungcheol Shin, Minkyu Je, Kwyro Lee, 2002 .

A concurrent dual-band CMOS low-noise amplifier for ISM-band application

Hyungcheol Shin, Hakchul Jung, Hee Sauk Jhon, 2008, 2008 International SoC Design Conference.

Analytical thermal noise model suitable for circuit design using short-channel MOSFETs

In Man Kang, Hyungcheol Shin, Kwyro Lee, 2005, 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers.

A miniaturized low-power wireless remote environmental monitoring system based on electrochemical analysis

Hyungcheol Shin, Kwyro Lee, Joonho Gil, 2004 .

FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

Hyungcheol Shin, Youngchang Yoon, Hochul Lee, 2007 .

Extracting accurate position and energy level of oxide trap generating random telegraph noise(RTN) in recessed channel MOSFET's

Hyungcheol Shin, Byung-Gook Park, Gyoyoung Jin, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

Hyungcheol Shin, Il Han Park, Kangyoon Lee, 2007, IEEE Transactions on Nanotechnology.

A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction

Hyungcheol Shin, Kwyro Lee, Minkyu Je, 2003, Microelectron. Reliab..

Extraction and modeling of physics-based gate resistance components in RF MOSFETs

Myounggon Kang, In Man Kang, Hyungcheol Shin, 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

MOS varactor modeling for mm-Wave applications

In Man Kang, Hyungcheol Shin, Hakchul Jung, 2008, 2008 Asia-Pacific Microwave Conference.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

Hyungcheol Shin, Jongwook Jeon, Byung-Gook Park, 2009, IEICE Trans. Electron..

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs

Hyungcheol Shin, Seongjae Cho, Youngchang Yoon, 2007, IEICE Trans. Electron..

40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication

Hyungcheol Shin, Kwyro Lee, Bonkee Kim, 1999 .

A low power low noise amplifier with subthreshold operation in 130 nm CMOS technology

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008 .

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

Myounggon Kang, Hyungcheol Shin, Il Han Park, 2011, IEEE Transactions on Electron Devices.

Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

Hyungcheol Shin, Jongwook Jeon, Bong Chan Kim, 2009, IEEE Transactions on Electron Devices.

Complete Quasi-Static Modeling of Accumulation Mode MOSFETs

Hyungcheol Shin, Jong Duk Lee, Keum-Dong Jung, 2007 .

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

Hyungcheol Shin, Changhwan Shin, Dyukyoung Moon, 2014, IEICE Electron. Express.

Cone-Type SONOS Flash Memory

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Electron Device Letters.

Optimization of cascode configuration in CMOS low‐noise amplifier

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008 .

Correction to “Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory” [Sep 13 1139-1141]

Hyungcheol Shin, Dong Hua Li, Yuchul Hwang, 2013 .

A New Extraction Method of Small-Signal Parameters of MOSFETs for RF Modeling

Hyungcheol Shin, Minkyu Je, Kwyro Lee, 2000 .

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEEE Electron Device Letters.

On the large-signal CMOS modeling and parameter extraction for RF applications

Hyungcheol Shin, Minkyu Je, Kwyro Lee, 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

Dumbbell-shaped Nanowire with Body Contact Region for Three Dimensional (3D) NAND Flash Memory Application

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2010 .

Electrical and Optical Isolation for Si FED : characterization and Improvement

Hyungcheol Shin, Jong Duk Lee, Jong-Ho Lee, 1997 .

Analytic approach to power-constrained CMOS low-noise amplifier design with figure of merit consideration

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))

Hyungcheol Shin, Hee Sauk Jhon, Seung Il Choi, 2005 .

A new small signal modeling of RF MOSFETs including charge conservation capacitances

Hyungcheol Shin, Minkyu Je, Kwyro Lee, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Write Characteristics of Silicon Resistive Probe

Hyungcheol Shin, Young Ho Jung, Jun-soo Kim, 2005 .

CMOS low-noise amplifer with noise suppression technique from gate resistance (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

Hyungcheol Shin, Hee Sauk Jhon, Ickhyun Song, 2007 .

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007, IEICE Trans. Electron..

Low Frequency Noise Characteristics of the 180㎚ MOSFETs

In Man Kang, Hyungcheol Shin, Hocheol Lee, 2005 .

Small size low noise amplifier with suppressed noise from gate resistance

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008 .

Bias and Device Optimization for 0.13-㎛ CMOS Low-Noise Amplifier Design

Hyungcheol Shin, Hakchul Jung, Hee Sauk Jhon, 2007 .

An Improved Concurrent Dual-Band CMOS Low Noise Amplifier

Hyungcheol Shin, Joonho Gil, Hee Sauk Jhon, 2005 .

Design optimization of a 10 GHz low noise amplifier with gate drain capacitance consideration in 65 nm CMOS technology

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Spectral reflectance as a non-destructive SIMOX quality evaluation technique

Hyungcheol Shin, Scott Wilson, Marco Racanelli, 1996, 1996 IEEE International SOI Conference Proceedings.

L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications

Hyungcheol Shin, Min-Chul Sun, Woo Young Choi, 2013, IEICE Trans. Electron..

A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique

Hyungcheol Shin, Kwyro Lee, Hongjae Jang, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Separate Extraction of Gate Resistance Components in RF MOSFETs

In Man Kang, Hyungcheol Shin, Myounggon Kang, 2007, IEEE Transactions on Electron Devices.

Simple wide-band on-chip inductor model for silicon-based RF ICs

Hyungcheol Shin, Joonho Gil, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

A New EEPROM with Side Floating Gates Having Different Work Function from Control Gate

Hyungcheol Shin, Jong-Ho Lee, Hoon Kim, 2002 .

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory

Hyungcheol Shin, Sangjin Kwon, Kyunghwan Lee, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Accurate four-terminal RF MOSFET model accounting for the short-channel effect in the source-to-drain capacitance

Hyungcheol Shin, Minkyu Je, M. Je, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

A Simple Figure of Merit of RF MOSFET for Low-Noise Amplifier Design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2008, IEEE Electron Device Letters.

A New SOI Inverter using Active Body-Bias

Hyungcheol Shin, Minkyu Je, Jong-Ho Lee, 1998 .

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008 .

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEICE Trans. Electron..

A Fully Integrated 6.5 GHz CMOS Low Noise Amplifier by using Logic Process

In Man Kang, Hyungcheol Shin, Joonho Gil, 2005 .

Linearity Optimization of DG MOSFET for RF application

Myounggon Kang, Hyungcheol Shin, Dong Hwee Kim, 2005 .

A new approach of NAND flash cell trap analysis using RTN characteristics

Hyungcheol Shin, Chang-Sub Lee, Young-Hyun Jun, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs

Hyungcheol Shin, Ickhyun Song, Youngchang Yoon, 2008, IEICE Trans. Electron..

Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures

Hyungcheol Shin, Byung-Gook Park, Il Han Park, 2006 .

Investigation of Thermal Noise Factor in Nanoscale MOSFETs

Hyungcheol Shin, Jongwook Jeon, Byung-Gook Park, 2010 .

An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008 .

A New Noise Parameter Model of Short-Channel MOSFETs

In Man Kang, Hyungcheol Shin, Jongwook Jeon, 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

Modeling of Lateral Migration Mechanism During the Retention Operation in 3D NAND Flash Memories

Myounggon Kang, Hyungcheol Shin, Jaeyeol Park, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Hyungcheol Shin, Byung-Gook Park, Daewoong Kang, 2008 .

Analytical Thermal Noise Model of Deep-submicron MOSFETs

Hyungcheol Shin, Jongwook Jeon, Se Young Kim, 2006 .

A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Investigation of mobility in twin silicon nanowire MOSFETs (TSNWFETs)

Hyungcheol Shin, Byung-Gook Park, Donggun Park, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Analysis of Failure Mechanisms and Extraction of Activation Energies $(E_{a})$ in 21-nm nand Flash Cells

Myounggon Kang, Hyungcheol Shin, Dong Hua Li, 2013, IEEE Electron Device Letters.

Low hysteresis pentacene thin-film transistors using SiO2/cross-linked poly(vinyl alcohol) gate dielectric

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2006 .

Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60 nm MOSFETs

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007 .

The effects of deuterium annealing on the reduction of dark currents in the CMOS APS

Hyungcheol Shin, S. S. Park, Byung-Gook Park, 2004, IEEE Transactions on Electron Devices.

Extraction of $\pi$-Type Substrate Resistance Based on Three-Port Measurement and the Model Verification up to 110 GHz

In Man Kang, Hyungcheol Shin, Jong Duk Lee, 2007, IEEE Electron Device Letters.

Characterization of Border Trap Density With the Multifrequency Charge Pumping Technique in Dual-Layer Gate Oxide

Hyungcheol Shin, Byoungchan Oh, Taewook Kang, 2011, IEEE Transactions on Electron Devices.

Extraction of trap energy and location from random telegraph noise in gate leakage current (Ig RTN) of metal–oxide semiconductor field effect transistor (MOSFET)

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010 .

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

Hyungcheol Shin, Sung-Joo Hong, Seon-Yong Cha, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Modeling of apparent activation energy and lifetime estimation in NAND flash memory

Myounggon Kang, Hyungcheol Shin, Yuchul Hwang, 2015 .

Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

Hyungcheol Shin, Byung-Gook Park, Young June Park, 2011, IEEE Transactions on Electron Devices.

Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory

Myounggon Kang, Hyungcheol Shin, Yuchul Hwang, 2014, IEEE Electron Device Letters.

Full-Swing a-IGZO Inverter With a Depletion Load Using Negative Bias Instability Under Light Illumination

Hyungcheol Shin, Byung-Gook Park, Hyuck-In Kwon, 2012, IEEE Electron Device Letters.

3-D stacked active layers and vertical gate NAND flash string with single-crystal Si channel by adopting Si/SiGe selective etch process

Hyungcheol Shin, Byung-Gook Park, Hyuck-In Kwon, 2010, 2010 Silicon Nanoelectronics Workshop.

Simultaneous Extraction of Locations and Energies of Two Independent Traps in Gate Oxide From Four-Level Random Telegraph Signal Noise

Hyungcheol Shin, Hochul Lee, Seungwon Yang, 2008 .

Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010, IEEE Electron Device Letters.

Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning

Hyungcheol Shin, Byung-Gook Park, Il Han Park, 2009, IEEE Transactions on Electron Devices.

Modeling and Parameter Extraction for the Series Resistance in Thin-Film Transistors

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009 .

Extraction of voltage transfer characteristic of inverter based on TSNWFETs

Hyungcheol Shin, Donggun Park, Sung Dae Suk, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Activation Energies $(E_{a})$ of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling

Myounggon Kang, Hyungcheol Shin, Dong Hua Li, 2013, IEEE Transactions on Electron Devices.

Compact Model Strategy of Metal-Gate Work-Function Variation for Ultrascaled FinFET and Vertical GAA FETs

Myounggon Kang, Hyungcheol Shin, Jongwook Jeon, 2019, IEEE Transactions on Electron Devices.

An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm nand Flash Technologies

Myounggon Kang, Hyungcheol Shin, Byung-Gook Park, 2012, IEEE Electron Device Letters.

Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

Hyungcheol Shin, Yuchul Hwang, Duckseoung Kang, 2015 .

Modeling of Lateral Migration Mechanism of Holes in 3D NAND Flash Memory Charge Trap Layer during Retention Operation

Hyungcheol Shin, Jaeyeol Park, 2019, 2019 Silicon Nanoelectronics Workshop (SNW).

Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation

Hyungcheol Shin, Min-Chul Sun, Byung-Gook Park, 2010, 2010 IEEE Nanotechnology Materials and Devices Conference.

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010 .

The Extraction and Analysis of Parasitic Resistance of Nanowire-FET

Myounggon Kang, Hyungcheol Shin, Hyungwoo Ko, 2017 .

Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs

Hyungcheol Shin, Heung-Jae Cho, Dong Seup Lee, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Myounggon Kang, Hyungcheol Shin, Wook-Ghee Hahn, 2011 .

Random Telegraph Noise in n-type and p-type silicon nanowire transistors

Hyungcheol Shin, Donggun Park, Kyoung Hwan Yeo, 2008, 2008 IEEE International Electron Devices Meeting.

Analysis of conduction mechanism in silicon nitride-based RRAM

Hyungcheol Shin, Byung-Gook Park, Sunghun Jung, 2014 .

$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

Hyungcheol Shin, Hee-Sauk Jhon, Byung-Gook Park, 2009, IEEE Electron Device Letters.

Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits

Hyungcheol Shin, Min-Chul Sun, Byung-Gook Park, 2012 .

Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory

Hyungcheol Shin, Yuchul Hwang, Dong Hua Li, 2013, IEEE Electron Device Letters.