S.H. Lewis

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

P.J. Hurst, C.R. Grace, S.H. Lewis, 2004, IEEE Journal of Solid-State Circuits.

An 8-bit 13-Msamples/s digital-background-calibrated algorithmic ADC

P.J. Hurst, O.E. Erdogan, S.H. Lewis, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

P.J. Hurst, Xiaoyue Wang, Haoyue Wang, 2009, IEEE Journal of Solid-State Circuits.

A Passive Switched-Capacitor Finite-Impulse-Response Equalizer

P.J. Hurst, S.H. Lewis, N.J. Guilar, 2007, IEEE Journal of Solid-State Circuits.

A 1.4 V Supply CMOS Fractional Bandgap Reference

T. R. Viswanathan, S.H. Lewis, R.T. Perry, 2006, IEEE Journal of Solid-State Circuits.

A mixed-signal RAM decision-feedback equalizer for disk drives

P.J. Hurst, S.H. Lewis, B.C. Rothenberg, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD

P.J. Hurst, O.E. Erdogan, S.H. Lewis, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

An 8b 80MSample/s pipelined ADC with background calibration

S.H. Lewis, Jun Ming, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

P.J. Hurst, S.H. Lewis, Xiaoyue Wang, 2004, IEEE Journal of Solid-State Circuits.

A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration

P.J. Hurst, Nick C.-J. Chang, S.H. Lewis, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A pipelined 9-stage video-rate analog-to-digital converter

S.H. Lewis, R. Ramachandran, H.S. Fetterman, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.