Masato Sakao

Logic based Embedded DRAM technologies targeting Low Voltage and High Speed Operation

I. Naritake, T. Sakoh, S. Arai, 2002 .

and Repair Function

Hiroki Koike, Masahide Takada, Hidenobu Miyamoto, 1990 .

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

Takamaro Kikkawa, Naoki Kasai, Masato Sakao, 1990, International Technical Digest on Electron Devices.

Self-Test and

Hiroki Koike, Toshio Takeshima, Masahide Takada, 1992 .

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Hiroki Koike, Takaho Tanigawa, Hidenobu Miyamoto, 1992 .

Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

Takaho Tanigawa, Yasushi Yamagata, Ken Inoue, 2006, IEEE Custom Integrated Circuits Conference 2006.

Overview and Future Challenges eDRAM Technologies

Takaho Tanigawa, K. Inoue, T. Sakoh, 2006 .