Bulusu Anand

发表

Timing model for two stage buffer and its application in ECSM characterization

Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, 2015, 2015 19th International Symposium on VLSI Design and Test.

Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

Bulusu Anand, S. K. Manhas, Archana Pandey, 2016, IEEE Transactions on Electron Devices.

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Bulusu Anand, Sudeb Dasgupta, Menka Yadav, 2013, Microelectron. J..

FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay

Bulusu Anand, S. K. Manhas, Archana Pandey, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies

Arvind Kumar Sharma, Bulusu Anand, Sudeb Dasgupta, 2015, 2015 19th International Symposium on VLSI Design and Test.

Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Baljit Kaur, Bulusu Anand, Sandeep Miryala, 2011, 2011 12th International Symposium on Quality Electronic Design.

An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective

Arvind Kumar Sharma, Bulusu Anand, Naushad Alam, 2018, 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

The impact of process-induced mechanical stress on multi-fingered device performance

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2012, Other Conferences.

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Bulusu Anand, Archana Pandey, Sudeb Dasgupta, 2014, IEEE Transactions on Electron Devices.

Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure

Bulusu Anand, Arvind Sharma, Naushad Alam, 2018, 2018 International Symposium on Devices, Circuits and Systems (ISDCS).

An energy-efficient variation aware self-correcting latch

Arvind Kumar Sharma, Bulusu Anand, Chaudhry Indra Kumar, 2019, Microelectron. J..

Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects

Brajesh Kumar Kaushik, Bulusu Anand, Manoj Kumar Majumder, 2012, VDAT.

An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis

Arvind Kumar Sharma, Bulusu Anand, Sayyaparaju Sagar Varma, 2016, 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

Mohit Sharma, Bulusu Anand, S. K. Manhas, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges

Bulusu Anand, Sudeb Dasgupta, 2015, 2015 28th International Conference on VLSI Design.

Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic

Bulusu Anand, S. K. Manhas, Sudeb Dasgupta, 2014, IEEE Transactions on Nanotechnology.

An accurate current source model for CMOS based combinational logic cell

Baljit Kaur, Bulusu Anand, S. K. Manhas, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

An Efficient and Accurate Variation-Aware Design Methodology for Near-threshold MOS-Varactor based VCO Architectures

Bulusu Anand, Neeraj Mishra, Lalit Mohan Dani, 2020 .

Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability

Bulusu Anand, Chaudhry Indra Kumar, B. Anand, 2018, 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2012, VDAT.

The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2013, Microelectron. Reliab..

Lateral silicon nanowire based standard cell design for higher performance

Mohit Sharma, Bulusu Anand, S. K. Manhas, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasitics

Bulusu Anand, Vr Rao, Mp Desai, 2007 .

Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability

Baljit Kaur, Bulusu Anand, S. K. Manhas, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand, 2016, Microelectron. J..

A modified method of logical effort for FinFET circuits considering impact of fin-extension effects

Bulusu Anand, Archana Pandey, Shobhit Tyagi, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance

Mohit Sharma, Bulusu Anand, Satish Maheshwaram, 2017, VDAT.

High performance energy efficient radiation hardened latch for low voltage applications

Bulusu Anand, Chaudhry Indra Kumar, 2019, Integr..

A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design

Bulusu Anand, Chaudhry Indra Kumar, B. Anand, 2020, IEEE Transactions on Device and Materials Reliability.

A novel energy-efficient self-correcting methodology employing INWE

Arvind Kumar Sharma, Bulusu Anand, Sandeep Miryala, 2016, 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Efficient static D-latch standard cell characterization using a novel setup time model

Bulusu Anand, Sudeb Dasgupta, Yogendra Sharma, 2015, Sixteenth International Symposium on Quality Electronic Design.

A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz

Bulusu Anand, Sudeb Dasgupta, Arnab Kumar Biswas, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2012, 2012 International Symposium on Electronic System Design (ISED).

An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect

Arvind Kumar Sharma, Bulusu Anand, Bijay Kumar Dalai, 2014, 18th International Symposium on VLSI Design and Test.

MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques

Bulusu Anand, Neeraj Mishra, Lalit Dani, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor

Bulusu Anand, Vivek Asthana, Sudeb Dasgupta, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies

Baljit Kaur, Bulusu Anand, S. K. Manhas, 2013, International Symposium on Quality Electronic Design (ISQED).

The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices

Bulusu Anand, Sudeb Dasgupta, Naushad Alam, 2013, Microelectron. Reliab..

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

Bulusu Anand, Chaudhry Indra Kumar, 2019, IEEE Transactions on Nuclear Science.

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization

Ajoy Mandal, Bulusu Anand, Sudeb Dasgupta, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect

Bulusu Anand, Nitanshu Chauhan, Shashank Banchhor, 2021, 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID).

Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

Bulusu Anand, S. K. Manhas, Gaurav Kaushal, 2013, IEEE Transactions on Electron Devices.