Xiaoheng Chen

High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm

Xiaoheng Chen, Chung-Li Wang, Xiaoheng Chen, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

Shu Lin, Venkatesh Akella, Jingyu Kang, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes

Zongwang Li, Shaohua Yang, Xiaoheng Chen, 2012, IEEE Transactions on Communications.

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

Venkatesh Akella, Xiaoheng Chen, V. Akella, 2011, TRETS.

Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes

Shu Lin, Venkatesh Akella, Jingyu Kang, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes

Shu Lin, Venkatesh Akella, Xiaoheng Chen, 2009, 2009 47th Annual Allerton Conference on Communication, Control, and Computing (Allerton).

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing

Shu Lin, Venkatesh Akella, Jingyu Kang, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

Shu Lin, Venkatesh Akella, Xiaoheng Chen, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.