H. Pilo

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

H. Pilo, C. Barwin, G. Braceras, 2007, IEEE Journal of Solid-State Circuits.

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

A. Roberts, H. Pilo, G. Braceras, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin

J. Covino, H. Pilo, S. Lamphier, 2000, IEEE Journal of Solid-State Circuits.

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

H. Pilo, G. Braceras, S. Lamphier, 2009, IEEE Journal of Solid-State Circuits.

A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process

H. Pilo, S. Lamphier, F. Towler, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

S. Burns, A. Roberts, H. Pilo, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin

H. Pilo, S. Lamphier, T. Traver, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).