T. Sasaki

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Masahide Matsumoto, Hirofumi Inoue, Takeshi Yamaguchi, 2014, IEEE Journal of Solid-State Circuits.