Chi-Hsin Chiu

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

Xin Wu, Suresh Ramalingam, Steve Chiu, 2014 .

Development of 25-$\mu{\rm m}$ -Pitch Microbumps for 3-D Chip Stacking

A. Kumar, V. Kripesh, Aibin Yu, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Development of thermal compression bonding with Non Conductive Paste for 3DIC fine pitch copper pillar bump interconnections

Mike Ma, Steve Chiu, Mu-Hsuan Chan, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

A. Kumar, D. Pinjala, J. H. Lau, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

A. Kumar, V. Kripesh, Aibin Yu, 2008, 2008 10th Electronics Packaging Technology Conference.

Sub-modeling technique for thermo-mechanical simulation of solder microbumps assembly in 3D chip stacking

Dim-Lee Kwong, V. Kripesh, Aibin Yu, 2009, 2009 11th Electronics Packaging Technology Conference.

Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps

John H. Lau, Aibin Yu, Vaidyanathan Kripesh, 2009, 2009 59th Electronic Components and Technology Conference.