M. Jagadesh Kumar

Global University Rankings: What should India do?

M. Jagadesh Kumar, M. Kumar, 2015 .

Double gate symmetric tunnel FET: investigation and analysis

M. Jagadesh Kumar, Sindhu Ramaswamy, M. Kumar, 2017, IET Circuits Devices Syst..

IETE Technical Review — A Rising International Journal from India

M. Jagadesh Kumar, 2016 .

Even Brilliant Ideas are Never New: The Need to Cite References in a Research Paper

M. Jagadesh Kumar, 2014 .

Exploring the novel characteristics of fully depleted dual-material gate (DMG) SOI MOSFET using two-dimensional numerical simulation studies

M. Jagadesh Kumar, Anurag Chaudhry, 2004, 17th International Conference on VLSI Design. Proceedings..

DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions

M. Jagadesh Kumar, Rajat Vishnoi, Pratyush Panday, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Phase Change Memory Faults

Ali A. Orouji, M. Jagadesh Kumar, 2006, VLSI Design.

On the iterative schemes to obtain base doping profiles for reducing base transit time in a bipolar transistor

M. Jagadesh Kumar, V. S. Patri, 2001 .

Novel Ge-profile design for high-speed SiGe HBTs: modelling and analysis

M. Jagadesh Kumar, M. Kumar, V. S. Patri, 1999 .

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

M. Jagadesh Kumar, G. V. Reddy, 2005 .