M. Vasilko

Yield enhancements of design-specific FPGAs

Peter Y. K. Cheung, George A. Constantinides, Nicola Campregher, 2006, FPGA '06.

Yield modelling and yield enhancement for FPGAs using fault tolerance schemes

Peter Y. K. Cheung, George A. Constantinides, Nicola Campregher, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Peter Y. K. Cheung, George A. Constantinides, Nicola Campregher, 2005, FPGA '05.

Design synthesis for dynamically reconfigurable logic systems

Milan Vasilko, M. Vasilko, 2000 .

DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems

Milan Vasilko, M. Vasilko, 1999, FPL.

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs

Peter Y. K. Cheung, George A. Constantinides, Nicola Campregher, 2006, 2006 International Conference on Field Programmable Logic and Applications.

BIST Based Interconnect Fault Location for FPGAs

Peter Y. K. Cheung, Nicola Campregher, Milan Vasilko, 2004, FPL.

On Feasibility of FPGA Bitstream Compression During Placement and Routing

Milan Vasilko, Piotr Stepien, P. Stȩpień, 2006, 2006 International Conference on Field Programmable Logic and Applications.