T. Iwata

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current

Hiroyuki Yamauchi, Toru Iwata, Akito Uno, 1995, IEEE J. Solid State Circuits.

A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's

Hiroyuki Yamauchi, Toshiaki Tsuji, Toru Iwata, 1993 .