Hiroharu Fujise

Tolerance-based process proximity correction (PPC) verification methodology

Kohji Hashimoto, Shigeki Nojima, Takahiro Ikeda, 2004, Photomask Japan.

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Shoji Mimotogi, Masaki Satake, Takayuki Uchiyama, 2009, Advanced Lithography.

Feasibility of ultra-low k1 lithography for 28nm CMOS node

Soichi Inoue, Shoji Mimotogi, Hideaki Harakawa, 2009, Advanced Lithography.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

Soichi Inoue, Shoji Mimotogi, Masafumi Asano, 2008, Lithography Asia.

Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um2

Shoji Mimotogi, Masafumi Asano, Seiji Nagahara, 2007, SPIE Advanced Lithography.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

Soichi Inoue, Shoji Mimotogi, Masafumi Asano, 2008, SPIE Advanced Lithography.

Immersion resist process for 32-nm node logic devices

Shoji Mimotogi, Koutarou Sho, Shinichi Ito, 2008, SPIE Advanced Lithography.

Optical lithography technologies for 45-nm node CMOS

Kohji Hashimoto, Shoji Mimotogi, Suigen Kyoh, 2004, SPIE Advanced Lithography.