M. Ohta

Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

Shigeyoshi Watanabe, Yukihito Oowaki, Daisaburo Takashima, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology

Shigeru Kawanaka, M. Ohta, Tsuneaki Fuse, 2003, IEEE J. Solid State Circuits.

Word-line architecture for highly reliable 64-Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1992 .

New nibbled-page architecture for high-density DRAMs

Shigeyoshi Watanabe, Yukihito Oowaki, Takahiko Hara, 1989 .

300 Mbps level converters for 0.5 V system LSIs using FD/PD-SOI technology

Shigeru Kawanaka, M. Ohta, Tsuneaki Fuse, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Method for the detection of the sound isolation of double walls and the prediction of the output probability distribution with simultaneous existing background noise - especially traffic noise.

Yoshifumi Fujita, A. Ikuta, M. Ohta, 1989 .

Word-line Architecture For Constant Reliability 64Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1991, 1991 Symposium on VLSI Circuits.

DC integration level analysis of low-Vdd CMOS circuit using worst-case noise margin map

M. Ohta, A. Kameyama, Tsuneaki Fuse, 2001, 2001 6th International Workshop on Statistical Methodology (Cat. No.01TH8550).

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

The stabilized reference-line (SRL) technique for scaled DRAMs

Yukihito Oowaki, Fujio Masuoka, Daisaburo Takashima, 1990 .

A 33-ns 64-Mb DRAM

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1991 .