W. Rausch

发表

Parameter studies concerning the flow behaviour of a pebble with reference to the fuel element movement in the core of the THTR 300 MWe prototype reactor

D. Bedenig, G. Schmidt, W. Rausch, 1968 .

Partially-depleted SOI technology for digital logic

E. Leobandung, G.G. Shahidi, F. Assaderaghi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

DEVELOPMENT OF HIGH-TEMPERATURE THERMAL REACTORS IN GERMANY.

R. Schulten, W. Rausch, R. Hecker, 1967 .

EXPERIMENTAL RESULTS WITH THE INDIVIDUALIZER DISC-SCRAP SEPARATOR COMBINATION.

W. Rausch, C. B. von der Decken, R. Faber, 1969 .

THE HTR--CONSTRUCTION LINE WITH ADVANCED CONVERTER REACTORS.

H. W. Mueller, U. Hennings, W. Rausch, 1970 .

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

M. Sherony, J. Sleight, G. Shahidi, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

History dependence of non-fully depleted (NFD) digital SOI circuits

R. Dennard, G.G. Shahidi, W. Rausch, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs

S. Narasimha, G. Freeman, W. Rausch, 2009, IEEE Transactions on Electron Devices.

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

A high performance epitaxial SiGe-base ECL BiCMOS technology

J.M.C. Stork, J. D. Cressler, S. Ratanaphanyarat, 1992, 1992 International Technical Digest on Electron Devices Meeting.

A 7.9/5.5 psec room/low temperature SOI CMOS

E. Leobandung, L. Wagner, F. Assaderaghi, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

M. Sherony, S. Narasimha, Y. Kohyama, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Mainstreaming of the SOI technology

M. Sherony, E. Leobandung, D. Moy, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

D. Mocuta, Y. Toyoshima, B.H. Lee, 2003, IEEE International Electron Devices Meeting 2003.

A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM

R. Flaker, S. Ratanaphanyarat, E. Leobandung, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Effect of emitter contact materials on high-performance vertical p-n-p transistors

S. Ratanaphanyarat, W. Rausch, J.O. Chu, 1991, IEEE Electron Device Letters.