Junwhan Ahn

发表

A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones

Sungjoo Yoo, Mungyu Son, Junwhan Ahn, 2015, 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

A novel zero weight/activation-aware hardware architecture of convolutional neural network

Dongyoung Kim, Sungjoo Yoo, Junwhan Ahn, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Fast Generation of Multiple Custom Instructions under Area Constraints

Kiyoung Choi, Di Wu, Junwhan Ahn, 2011 .

Dynamic power management of off-chip links for Hybrid Memory Cubes

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Differential Write-Conscious Software Design on Phase-Change Memory

Sunggu Lee, Sungjoo Yoo, Hyunsun Park, 2016, ACM Trans. Design Autom. Electr. Syst..

Resource-shared custom instruction generation under performance/area constraints

Di Wu, Kiyoung Choi, Junwhan Ahn, 2012, 2012 International Symposium on System on Chip (SoC).

Lower-bits cache for low power STT-RAM caches

Kiyoung Choi, Junwhan Ahn, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A polynomial-time custom instruction identification algorithm based on dynamic programming

Kiyoung Choi, Junwhan Ahn, Imyong Lee, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Memory fast-forward: A low cost special function unit to enhance energy efficiency in GPU for big data processing

Sunggu Lee, Sungpack Hong, Eunhyeok Park, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Weighted-Entropy-Based Quantization for Deep Neural Networks

Eunhyeok Park, Sungjoo Yoo, Junwhan Ahn, 2017, 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR).

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016, IEEE Transactions on Computers.

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Kiyoung Choi, Junwhan Ahn, Junwhan Ahn, 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture

Kiyoung Choi, Onur Mutlu, Sungjoo Yoo, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM

Kiyoung Choi, Junwhan Ahn, Woong Seo, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization

Kiyoung Choi, Junwhan Ahn, Junwhan Ahn, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Write intensity prediction for energy-efficient non-volatile caches

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem

Kiyoung Choi, Dongwoo Lee, Junwhan Ahn, 2012, 2012 International SoC Design Conference (ISOCC).

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

Locality-aware vertex scheduling for GPU-based graph computation

Eunhyeok Park, Sungjoo Yoo, Hyunsun Park, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures

Kiyoung Choi, Jinho Lee, Junwhan Ahn, 2015, The 20th Asia and South Pacific Design Automation Conference.

ZeNA: Zero-Aware Neural Network Accelerator

Dongyoung Kim, Sungjoo Yoo, Junwhan Ahn, 2018, IEEE Design & Test.

Making DRAM stronger against row hammering

Sungjoo Yoo, Hyunsun Park, Mungyu Son, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Benzene

Kiyoung Choi, Soojung Ryu, Junwhan Ahn, 2018, ACM Trans. Archit. Code Optim..

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA

Kiyoung Choi, Junwhan Ahn, Kyuseung Han, 2013, TACO.

Zero and data reuse-aware fast convolution for deep neural networks on GPU

Dongyoung Kim, Sungjoo Yoo, Hyunsun Park, 2016, 2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Software-Defined Far Memory in Warehouse-Scale Computers

Jichuan Chang, Parthasarathy Ranganathan, Junwhan Ahn, 2019, ASPLOS.

AIM

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016 .

A scalable processing-in-memory accelerator for parallel graph processing

Kiyoung Choi, Onur Mutlu, Sungpack Hong, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

Kiyoung Choi, Junwhan Ahn, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Benzene

Kiyoung Choi, Soojung Ryu, Junwhan Ahn, 2018, Report on carcinogens : carcinogen profiles.

AIM

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016 .