S.K. Goel

A novel test time reduction algorithm for test architecture design for core-based system chips

S.K. Goel, E.J. Marinissen, E. Marinissen, 2002, Proceedings The Seventh IEEE European Test Workshop.

Data invalidation analysis for scan-based debug on multiple-clock system chips

B. Vermeulen, S.K. Goel, 2002, Proceedings The Seventh IEEE European Test Workshop.

Test infrastructure design for the Nexperia/spl trade/ home platform PNX8550 system chip

Kuoshu Chiu, T. Nguyen, S.K. Goel, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Core-based scan architecture for silicon debug

B. Vermeulen, S.K. Goel, T. Waayers, 2002, Proceedings. International Test Conference.